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Senior ASIC Layout Design Engineer Jobs in Santa Clara, CA

14 Jobs

  • 3.5
    Advanced Micro Devices, Inc. – Santa Clara, CA
    $106k-$144k(Glassdoor est.)
    NEW
    join our team. AMD's GPU design team is seeking an experienced ASICDesignEngineer to design the execution control for the… for a designengineer in AMD's graphics group working on next generation graphics architectures. Our focus is on design of the…
  • 3.9
    Palo Alto Networks – Santa Clara, CA
    $78k-$100k(Glassdoor est.)
    HOT
    hardware including Board, FPGA and ASIC. You will be working on our Board Hardware team who designs and tests printed circuit assemblies… Manage and review PCB layout Learn about the complete hardware design cycle including schematic, layout, and test Skills…
  • 3.4
    Dialog Semiconductor – Campbell, CA
    $101k-$136k(Glassdoor est.)
    17 days ago 17d
    and post layout verification. Collaboration with analog engineers and test engineers on analog testability design and debugging… continued growth, we seek a Senior Digital DesignEngineer. The role Working in the Digital Design - Power Conversion Business…
  • 3.5
    Encore Semi Inc. – Santa Clara, CA
    $132k-$169k(Glassdoor est.)
    14 days ago 14d
    Position Title: Senior/Staff Hardware DesignEngineer Work Location: Bay Area, CA Status: Full-Time Employment (W2) Full… collaborate with customers to design, verify and bring up new boards to support new RF focused FPGA and ASIC products. You will build…
  • Seagate Technology LLC – Fremont, CA
    $77k-$117k(Glassdoor est.)
    15 days ago 15d
    mixed-analog/digital CMOS integrated circuit layouts, as directed by ASICDesignEngineers. The role will have circuit / block-level… 171504 Sr. ASIC Mask DesignEngineer (Open) Seagate delivers advanced digital storage solutions to meet the needs of today's…
  • Advanced Technology Search – San Jose, CA
    $91k-$126k(Glassdoor est.)
    10 days ago 10d
    Job Description ASIC/IP Verification EngineerASIC/LayoutDesignEngineer: Oversees definition, design, verification, and… development, part of the ASIC solution for storage applications. They are looking for a Senior Verification Engineer, who will be a key…
  • 3.0
    Seagate Technology – Fremont, CA
    20 days ago 20d
    171279 Senior Staff Physical LayoutDesigner (Open) Seagate delivers advanced digital storage solutions to meet the needs… , timing analysis and ASIC physical design methodology for large scale VLSI design. Experience/Education: Seeking candidates…
  • 3.2
    Rambus – Sunnyvale, CA
    $74k-$100k(Glassdoor est.)
    13 days ago 13d
    collaborate with the industry, partnering with leading ASIC and SoC designers, foundries, IP developers, EDA companies and validation… collaborate with the industry, partnering with leading ASIC and SoC designers, foundries, IP developers, EDA companies and validation…
  • 3.0
    Seagate Technology – Fremont, CA
    $96k-$131k(Glassdoor est.)
    19 days ago 19d
    mixed-analog/digital CMOS integrated circuit layouts, as directed by ASICDesignEngineers. The role will have circuit / block-level… with senior internal and external personnel in own area of expertise. Requirements: The Sr. ASIC Mask DesignEngineer is not…
  • 3.9
    ASML – San Jose, CA
    $76k-$106k(Glassdoor est.)
    20 days ago 20d
    module level Analog and mixed signal ASICdesign and tapeout Analog and mixed signal ASIC PCB level integration Education… signal circuit design and circuit simulation in both board level and IC level, print circuit board (PCB) layout, PCB prototyping…
  • 3.7
    MediaTek – San Jose, CA
    $78k-$104k(Glassdoor est.)
    21 days ago 21d
    for TCAM and SRAM memory design for high performance data center switches and network ASICs. Design and implement a high performance… coordinate layout activities Knowledge of transistor level STA tools such as Nanotime Ability to come up with design verification…
  • 3.9
    Infineon Technologies – Milpitas, CA
    14 days ago 14d
    Infrastructure Sensing and includes Design and Development of Control ICs, Customized chips (ASICs), Discrete low-voltage and high-… point-of-load controllers. The design-in activities at key customers includes schematic & layout reviews, board bring up and full…
  • 3.5
    Cavium, Inc. – San Jose, CA
    $192k-$280k(Glassdoor est.)
    6 days ago 6d
    know-how for engineering tasks including component selection, AVL enablement, design reviews of schematic/layout/DFM review and… development partners. Requirements: Expertise with ASIC/SOC design, validation process and management of ODM/OEM projects…
  • 3.3
    Finisar – Sunnyvale, CA
    11 days ago 11d
    DUTIES & RESPONSIBILITIES: This is a seniorengineer position responsible for designing and developing high speed fiber optics… mechanical, RF design, assembly process, test engineering, and product engineering teams. Responsible for the concept design, EVT, and…
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