Senior ASIC Layout Design Engineer Jobs in Santa Clara, CA | Glassdoor

Senior ASIC Layout Design Engineer Jobs in Santa Clara, CA

19 Jobs
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  • 3.9
    Infinera – Sunnyvale, CA
    Est. Salary $143k-$183k
    6 days ago 6d
    guidelines to layout engineers, need to be hands on in drawing layout if necessary; Be meticulous about all design and layout details… new or junior circuit designers and layout engineers; Independently resolves issues and conquer design challenges; Self-motivated…
  • 3.8
    Nokia – Sunnyvale, CA
    1 days ago 1d
    transceivers • Custom IC layout, in deep submicron CMOS at and below 65 nm node • Experience in module design preferred (Experience… transceivers • Custom IC layout, in deep submicron CMOS at and below 65 nm node • Experience in module design preferred (Experience…
  • 4.3
    NVIDIA – Santa Clara, CA
    19 days ago 19d
    products. As a senior team member, you will collaborate closely with Architecture, Software, ASIC, VLSI, DFT, Layout, and Product… We are now looking for a Senior ASIC Power Engineer: In this role you will be responsible for crafting and implementing the…
  • 3.0
    Fluke Corporation – Santa Clara, CA
    Est. Salary $95k-$125k
    12 days ago 12d
    The ASIC Mixed Signal engineer will be a member of the ASIC team in Santa Clara that interacts with Analog/circuit designers, digital… verilogA and .lib models for custom macro SAR ADC design, floor plan and layout Development AMS simulation environment at block…
  • 3.0
    Tektronix – Santa Clara, CA
    Est. Salary $113k-$147k
    12 days ago 12d
    The ASIC Mixed Signal engineer will be a member of the ASIC team in Santa Clara that interacts with Analog/circuit designers, digital… verilogA and .lib models for custom macro SAR ADC design, floor plan and layout Development AMS simulation environment at block…
  • 3.1
    Fortive – Santa Clara, CA
    Est. Salary $97k-$127k
    11 days ago 11d
    The ASIC Mixed Signal engineer will be a member of the ASIC team in Santa Clara that interacts with Analog/circuit designers, digital… verilogA and .lib models for custom macro * SAR ADC design, floor plan and layout * Development AMS simulation environment at block…
  • GigPeak – San Jose, CA
    EASY APPLY
    Est. Salary $106k-$155k
    2 days ago 2d
    Senior ASIC Design Engineer (Job Code WL) REPORTS TO: Director of ASIC Engineering LOCATION: San Jose, CA CLASSIFICATION:… currently seeking a Senior ASIC Design Engineer. Essential Duties and Responsibilities Management of ASIC design development Meet…
  • 3.4
    Advanced Micro Devices, Inc. – Sunnyvale, CA
    Est. Salary $86k-$128k
    11 days ago 11d
    modeling, analysis, & microarchitecture development. Senior ASIC/Layout Design Engineer CA0517: Responsible for functional verification… level logic design, floor plan, wire-plan, routing, layout, & formal verification. MTS ASIC/Layout Design Engineer CA0317: Perform…
  • 3.6
    Intel – Santa Clara, CA
    1 days ago 12hr
    implications of the silicon/FPGA design decisions. Preferred Skills: Experience with ASIC & FPGA based designs Experience with top… multidimensional designs involving the layout of complex integrated circuits. Performs all aspects of the SoC design flow from high-level…
  • 3.8
    ASML – San Jose, CA
    Est. Salary $68k-$95k
    6 days ago 6d
    module level Analog and mixed signal ASIC design and tapeout Analog and mixed signal ASIC PCB level integration Education Ph.D… signal circuit design and circuit simulation in both board level and IC level, print circuit board (PCB) layout, PCB prototyping…
  • 2.6
    Theranos – Palo Alto, CA
    Est. Salary $106k-$141k
    15 days ago 15d
    Electrical Engineering (BSEE) or MSEE (preferred) with 8+ years of industry experience., Must have proven design and development… expertise that are preferred include: Wireless communications, FPGA, ASIC, and signal processing., Experience using a digital simulation…
  • 4.1
    Cadence Design Systems – San Jose, CA
    Est. Salary $89k-$125k
    6 days ago 6d
    processing ASICs and FPGAs, and is interested in establishing SI/PI system budgets and implementing the advanced design validation… coding, and FEC algorithms. Working knowledge of PCB design and layout, as it impacts signal and power integrity. Working knowledge…
  • 3.6
    Intel – San Jose, CA
    Est. Salary $96k-$133k
    26 days ago 26d
    electrical engineering or computer science, with 5 years of experience 3 years of experience in ASIC, Custom block design and SoC… Responsibilities may include: the design of chip layout circuit design, circuit checking, device evaluation and characterization, documentation…
  • Cadence – San Jose, CA
    Est. Salary $72k-$102k
    11 days ago 11d
    processing ASICs and FPGAs, and is interested in establishing SI/PI system budgets and implementing the advanced design validation… coding, and FEC algorithms. * Working knowledge of PCB design and layout, as it impacts signal and power integrity. * Working…
  • 3.8
    Nokia – Sunnyvale, CA
    Est. Salary $150k-$204k
    1 days ago 1d
    General Purpose: Works in senior engineering role in product, system or technology program in SW/HW/System Design or Integration & Verification… • Custom IC layout, in 130nm SOI or deep submicron CMOS at and below 65 nm node • Experience in module design preferred (Experience…
  • 3.0
    Amazon Lab126 – Sunnyvale, CA
    Est. Salary $137k-$181k
    11 days ago 11d
    developing off-the-shelf and custom/semi-custom ASICs and SoCs for use * Design reference hardware for the product execution teams… new technologies * Perform schematic design and work with the CAD team on PCB layout * Assist in board bring-up and work…
  • 4.3
    NEXTEV – San Jose, CA
    Est. Salary $118k-$165k
    13 days ago 13d
    automotive industry is preferred, but not required FPGA and ASIC design About NIO (A brand owned by NextEV USA, Inc.) Were the… as well as experience in working directly with PCB Layout engineers Layout, routing experience Experience working closely with…
  • 3.1
    hermes-microvision – San Jose, CA
    EASY APPLY
    Est. Salary $80k-$111k
    15 days ago 15d
    module level Analog and mixed signal ASIC design and tapeout Analog and mixed signal ASIC PCB level integration Requirements… electrical engineering or related fields. Hands-on experiences of schematic capture, schematic level simulation, PCB layout, PCB level…
  • 3.8
    Logitech – Newark, CA
    Est. Salary $145k-$198k
    13 days ago 13d
    electro-mechanical parts, electrical board outlines and layouts, electrical design analysis, assistance in definition of assembly methods… system validation effort for engineering designs Design of product level policies and behaviors relying on lower level imaging…
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