Job Type
Date Posted
Salary Range
Distance

Senior DSP/Rtl Design Engineer Jobs in Santa Clara, CA

13 Jobs

  • Approgence – Santa Clara, CA
    24 days ago 24d
    Description : We are looking for a senior expert in SoC Physical Design and RTL Delivery Management for advanced modem Baseband… Job Title : SoC Physical Design and RTL Delivery Lead / Principal Engineer Job Location : Santa Clara, CA Job Description…
  • 5.0
    Tarana Wireless – Santa Clara, CA
    EASY APPLY
    $98k-$127k(Glassdoor est.)
    9 days ago 9d
    AND RESPONSIBILITIES: RTLdesign of digital circuits using VHDL or System Verilog Frontend design development and integration… verification RTLdesign and integration of large functional blocks in the modem - Development, assessment and refinement of RTL design…
  • 3.8
    Marvell Technology – Santa Clara, CA
    $96k-$143k(Glassdoor est.)
    18 days ago 18d
    Excellent DSP and Systems DesignEngineering opportunity to work on challenging ultra high-speed communication systems, focusing… architecture and lab test plan Work with design team to perform bit true match for RTL Lab testing and debug Must Have…
  • 3.7
    Lockheed Martin – Sunnyvale, CA
    $90k-$121k(Glassdoor est.)
    1 days ago 22hr
    Develop RTL utilizing a hardware description language (e.g. VHDL, Verilog, and/or SystemVerilog) and debug the design via simulation… Develop RTL utilizing a hardware description language (e.g. VHDL, Verilog, and/or SystemVerilog) and debug the design via simulation…
  • 3.7
    Lockheed Martin – Sunnyvale, CA
    $90k-$119k(Glassdoor est.)
    NEW
    FPGA Designer: The Senior ASIC/FPGA DesignEngineer will be working in the RF Center of Excellence (RF CoE). The Senior FPGA/… Develop RTL utilizing a hardware description language (e.g. VHDL, Verilog, and/or System Verilog) and debug the design via simulation…
  • 3.7
    Lockheed Martin – Sunnyvale, CA
    $136k-$178k(Glassdoor est.)
    NEW
    Digital Processor ASIC/FPGA Designer: The Senior Staff ASIC/FPGA DesignEngineer will be working in the RF Center of Excellence… Develop RTL utilizing a hardware description language (e.g. VHDL, Verilog, and/or System Verilog) and debug the design via simulation…
  • 3.7
    Lockheed Martin – Sunnyvale, CA
    $90k-$121k(Glassdoor est.)
    NEW
    Develop RTL utilizing a hardware description language (e.g. VHDL, Verilog, and/or SystemVerilog) and debug the design via simulation… Develop RTL utilizing a hardware description language (e.g. VHDL, Verilog, and/or SystemVerilog) and debug the design via simulation…
  • 3.9
    Xilinx – San Jose, CA
    $138k-$204k(Glassdoor est.)
    HOT
    through their design process Provide onsite support, and solve real time problems including software tool issues, RTL and simulation… FPGA-based architecture definition, design, and support (High Speed Serial IO, Embedded Processor, or DSP knowledge a plus) Fundamental…
  • 3.8
    Intel – San Jose, CA
    5 days ago 5d
    Electrical Engineering, Computer Engineering 6 year experience in DFT design and verification including both RTL and gate level… motivated senior DFx engineer to join an industry leading IC design team. This is an opportunity to work on cutting edge designs including…
  • 3.6
    Broadcom – San Jose, CA
    $92k-$125k(Glassdoor est.)
    26 days ago 26d
    firmware design customer support The following technical skills are required: Verilog RTLdesign with a strong… thrive in this role include: SERDES-based designs & DSP-hardware designs (EDC, PAM, QPSK, QAM) Implementing networking…
  • 2.9
    Avago Technologies – San Jose, CA
    $97k-$132k(Glassdoor est.)
    28 days ago 28d
    firmware design customer support The following technical skills are required: Verilog RTLdesign with a strong… thrive in this role include: SERDES-based designs & DSP-hardware designs (EDC, PAM, QPSK, QAM) Implementing networking…
  • 2.7
    SK Hynix Memory Solutions – San Jose, CA
    9 days ago 9d
    available for an FPGA designer to get involved in the implementation of ECC and SSD as well as other DSP algorithms on IC. The… Generating the specifications for FPGA platform, developing Verilog RTL code, defining verification methodology, building a test bench…
  • 2.7
    SK Hynix Memory Solutions – San Jose, CA
    $102k-$141k(Glassdoor est.)
    25 days ago 25d
    Computer Science Strong Verilog RTL, SystemC or C/C++, shell scripting skills ECC/DSP experience is highly desirable, but not required… throughput, power, area, performance for IP development DesignRTL code using Verilog Provide timing constraints, run synthesis…
Page 1 of 1
Unlock Your Free Employer Account