Senior DSP/Rtl Design Engineer Jobs in Santa Clara, CA | Glassdoor
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Senior DSP/Rtl Design Engineer Jobs in Santa Clara, CA

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  • 4.0
    Inphi Corporation – Santa Clara, CA
    Est. Salary $116k-$155k
    22 days ago 22d
    Experience designing circuitry using RTL and/or programming FPGAs is a plus. Experience working closely with circuit designers is a… QualitiesAs an Inphi Coherent DSP Applications Engineer, you will: Engage closely with sales, engineering, and customer personnel…
  • Approgence – San Jose, CA
    Est. Salary $79k-$105k
    6 days ago 6d
    Job Title : Senior ASIC/ RTL Design Engineer with DSP Job Location : San Diego & San Jose, CA Job Description : This… baseband modem. - Modem ASIC Design team is responsible for physical layer micro-architecture definition, RTL implementation, synthesis…
  • 3.5
    Broadcom – San Jose, CA
    Est. Salary $87k-$119k
    15 days ago 15d
    firmware design customer support The following technical skills are required: Verilog RTL design with a strong… thrive in this role include: SERDES-based designs & DSP-hardware designs (EDC, PAM, QPSK, QAM) Implementing networking…
  • 3.7
    Intel – Santa Clara, CA
    7 days ago 7d
    authoring microarchitecture/design specifications and converting them to design Familiarity with RTL development cycle Additional… skills, experience having managed architecture, systems engineering and/or RTL development teams, a proven ability to develop and drive…
  • 4.0
    Inphi Corporation – Santa Clara, CA
    13 days ago 13d
    schedule and deliverables. Work with digital design engineering to debug test cases in RTL and Gate Level simulation environment.… looking for a Senior Staff Verification Engineer. The candidate must have proven record of verifying complex designs leading to successful…
  • 3.3
    Toshiba America Business Solutions – San Jose, CA
    Est. Salary $71k-$93k
    12 days ago 12d
    controller H/W architecture & design Proven experience in high performance and low power RTL design of complex modules Proven… technologies such as new ECCs (LDPC, BCH) CPUs, Host interfaces, DSP & high performance protocols. Participate in continuous improvement…
  • 3.7
    Intel – San Jose, CA
    13 days ago 13d
    motivated senior DFx engineer to join an industry leading IC design team. This is an opportunity to work on cutting edge designs including… processor, DSP, SERDES, IO, 2.5D multi-die packaging and other technologies that will drive future success. As a senior DFx (Testability…
  • 3.6
    Xilinx – San Jose, CA
    Est. Salary $132k-$195k
    9 days ago 9d
    through their design process · Provide onsite support, and solve real time problems including software tool issues, RTL and simulation… FPGA-based architecture definition, design, and support (High Speed Serial IO, Embedded Processor, or DSP knowledge a plus) Fundamental…
  • 3.4
    Cavium, Inc. – San Jose, CA
    Est. Salary $98k-$134k
    14 days ago 14d
    Vector DSP programming, optimization and debugging is a plus. Experience in working with ASIC design team to guide RTL implementation… Work closely with ASIC design team to design HW block architecture, verify and validate optimized RTL implementation. Work with…
  • 2.9
    Avago Technologies – San Jose, CA
    Est. Salary $92k-$125k
    17 days ago 17d
    firmware design customer support The following technical skills are required: Verilog RTL design with a strong… thrive in this role include: SERDES-based designs & DSP-hardware designs (EDC, PAM, QPSK, QAM) Implementing networking…
  • 3.9
    Lam Research – Fremont, CA
    Est. Salary $148k-$198k
    28 days ago 28d
    design, system engineering, control system design, complex PCBA, large scale RTL design Verilog or VHDL, A/D, DSP, FPGA, C/C++,… Embedded Systems Design, leading a team of hardware: analog, digital, FPGA, control system, and software engineers in design & integration…
  • 3.0
    Toshiba – San Jose, CA
    Est. Salary $103k-$133k
    30+ days ago 30d+
    , LDPC & Reed Solomon codes. Proficient in Design Specification writing & RTL design. In-depth knowledge of NAND Flash memories… , BCH) CPUs, Host interfaces, DSP & high performance protocols. Will oversee SOCs Physical design Investigation of the Emerging…
  • Approgence – Santa Clara, CA
    13 days ago 13d
    Description : - We are looking for a senior expert in SoC Physical Design and RTL Delivery Management for advanced modem Baseband… Job Title : SoC Physical Design and RTL Delivery Lead / Principal Engineer Job Location : Santa Clara, CA Job Description…
  • 3.8
    Cavium – San Jose, CA
    Est. Salary $103k-$142k
    30+ days ago 30d+
    Vector DSP programming, optimization and debugging is a plus. * Experience in working with ASIC design team to guide RTL implementation… Work closely with ASIC design team to design HW block architecture, verify and validate optimized RTL implementation. * Work…
  • Approgence – Santa Clara, CA
    Est. Salary $86k-$118k
    27 days ago 27d
    frontend and backend design engineers towards developing and delivering RTL for advanced high-speed and low latency transmitter/receiver… processing engine PD hardening for high-performance blocks. - Responsible for all aspects of physical implementation from RTL to GDS…
  • 3.0
    Toshiba – San Jose, CA
    Est. Salary $97k-$170k
    30+ days ago 30d+
    , LDPC & Reed Solomon codes. Proficient in Design Specification writing & RTL design. In-depth knowledge of NAND Flash memories… ) CPUs, Host interfaces, DSP & high performance protocols. Will oversee Flash and SOC Physical design Investigation of the Emerging…
  • Approgence – Santa Clara, CA
    Est. Salary $89k-$123k
    12 days ago 12d
    with strong understanding of DSP. - Must be able to collaborate with cross-geo, cross functional design and verification teams. -… Job Title : Senior FPGA/Validation/Verification Engineer (Native Spanish Speaker) Job Location : Santa Clara, CA Job…
  • Approgence – Santa Clara, CA
    Est. Salary $89k-$123k
    12 days ago 12d
    with strong understanding of DSP - Must be able to collaborate with cross-geo, cross functional design and verification teams - Must… Job Title : Senior FPGA/Validation/Verification Engineer (only Technical Women Candidates) Job Location : Santa Clara,…
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