Senior ASIC Physical Design Engineer Jobs | Glassdoor
  • All Jobs (115)

Senior ASIC Physical Design Engineer Jobs

Filters
Filters
  • 3.3
    Aricent – United States
    NEW
    MATLAB, modeling) Physical Layer Design (USB, HDMI, DDR, MIPI) Digital Design for Mixed Signal ASICs (PLL, Phase-Lock-Loop… disciplines: SoC Design (ASIC integration, Peripherals, Bus Design, DC/PC, LINT, PTSI) RTL Design (Functional/Structural…
  • 4.4
    SpaceX – Irvine, CA
    Est. Salary $108k-$142k
    6 days ago 6d
    life on Mars. SENIORASICDESIGNENGINEER RESPONSIBILITIES: As a SeniorDesignEngineer youll help design, implement and… FPGAs and/or ASICs. Participate in the micro architecture and design partition within the ASIC/FPGA. Implement design blocks using…
  • 3.4
    AMD – Boxborough, MA
    Est. Salary $99k-$135k
    5 days ago 5d
    with RTL designs/Coding styles Demonstrated technical expertise in functional verification of microprocessor/ASICdesigns. Working… -on-a-Chip (SoC) design methodology. The business unit features a strong team of engineers who have design wins in all major…
  • 3.9
    Nokia – Sunnyvale, CA
    Est. Salary $88k-$123k
    7 days ago 7d
    communications! We are now looking for Senior Specialist, 5G ASICPhysicalDesign to join our team. Key responsibilities… responsible for back-end ASICdesign including physical place and route, timing analysis and fixing, and physical verification. You will…
  • 5.0
    CMP.jobs – Austin, TX
    NEW
    mixed-signal designers developing ASICs for next generation MEMS based microphones. Participate in all aspects of design from concept… Master's in Electrical Engineering with 10+ years of experience or PhD in Electrical Engineering with 8+ years of experience…
  • 3.3
    Aricent – United States
    13 days ago 13d
    MATLAB, modeling) Physical Layer Design (USB, HDMI, DDR, MIPI) Digital Design for Mixed Signal ASICs (PLL, Phase-Lock-Loop… disciplines: SoC Design (ASIC integration, Peripherals, Bus Design, DC/PC, LINT, PTSI) RTL Design (Functional/Structural…
  • 4.4
    SpaceX – Redmond, WA
    Est. Salary $119k-$159k
    7 days ago 7d
    enabling human life on Mars. SENIORASICENGINEER RESPONSIBILITIES: Implement ASIC / SoCs / FPGAs for multiple products… Masters degree in engineering or math. ASIC / FPGA / SoC System integration experience. Strong Silicon/ASICdesign experience. One…
  • 3.4
    Tektronix – Santa Clara, CA
    Est. Salary $102k-$134k
    5 days ago 5d
    Responsibilities The ASIC Mixed Signal engineer will be a member of the ASIC team that interacts with Analog/circuit designers, digital/RTL… /industry experience in circuit and ASIC o Exposure to analog and mixed-signal IC design o Familiarity with standard interfaces…
  • 3.7
    Xilinx – San Jose, CA
    Est. Salary $121k-$178k
    9 days ago 9d
    Familiar with state of the art placement/routing/physical synthesis algorithms for ASICs and/or FPGAs. Expert with C , data structures… software engineer to be part of the Xilinx Vivado Physical Implementation team. This team is responsible for design, implementation…
  • 3.7
    Fortive – Santa Clara, CA
    Est. Salary $96k-$127k
    4 days ago 4d
    Responsibilities The ASIC Mixed Signal engineer will be a member of the ASIC team that interacts with Analog/circuit designers, digital/RTL… /industry experience in circuit and ASIC o Exposure to analog and mixed-signal IC design o Familiarity with standard interfaces…
  • Approgence – San Diego, CA
    Est. Salary $75k-$103k
    7 days ago 7d
    perform bit-exact simulation. Modem ASICDesign team is working with physicaldesignengineer to deliver netlist, spec timing constraints… Job Title : SeniorASIC/ RTL DesignEngineer with DSP Job Location : San Diego & San Jose, CA Job Description : This…
  • 3.4
    AMD – Boxborough, MA
    Est. Salary $99k-$135k
    5 days ago 5d
    RTL designs/Coding styles Demonstrated technical expertise in functional verification of microprocessor/ASICdesigns.… System-on-a-Chip (SoC) design methodology. The business unit features a strong team of engineers who have design wins in all major…
  • 1.0
    FirstPass Engineering – Phoenix, AZ
    6 days ago 6d
    analysis and insertion tools in the overall ASICdesign flow and complete all Test Design Rule Checks. Insert DFT logic, including… in architecture and hardware design. Hands on experience and a solid understanding of ASICdesign, synthesis, simulation and…
  • 3.5
    HRL – Malibu, CA
    EASY APPLY
    27 days ago 27d
    verify ASIC 2-D stitching, ASIC 3-D stacked hybrids comprising of vastly different PDKs. Interface with front end designers to assist… models. Verification techniques for mixed signal VLSI ASICdesigns. Proficient in perl/tcl/python or other scripting language…
  • 3.0
    Fluke Corporation – Santa Clara, CA
    Est. Salary $88k-$117k
    4 days ago 4d
    Responsibilities The ASIC Mixed Signal engineer will be a member of the ASIC team that interacts with Analog/circuit designers, digital/RTL… /industry experience in circuit and ASIC o Exposure to analog and mixed-signal IC design o Familiarity with standard interfaces…
  • 4.4
    SpaceX – Irvine, CA
    Est. Salary $102k-$140k
    22 days ago 22d
    leadership skills. As a senior verification Engineer youll help define the verification methodology for the complex ASICs and FPGAs. You… engineering. 8+ years of experience verifying complex ASICs / FPGAs. 5+ years of experience in ASIC / FPGA verification using…
  • 2.8
    SK Hynix Memory Solutions – San Jose, CA
    Est. Salary $103k-$142k
    NEW
    Work with PhysicalDesign team to implement design Qualifications: BS, MS or PhD degree in Electrical Engineering or Computer… perform timing analysis Work with Design Verification and emulation team to validate design Develop functional models for architectural…
  • 3.6
    Dialog Semiconductor – Campbell, CA
    Est. Salary $96k-$128k
    5 days ago 5d
    8+ years of direct experience in ASIC/IC design with deep knowledge of whole IC design flow from RTL coding and verification… either Verilog or VHDL RTL coding and ASICdesign methodology. Competence in developing design constraints for synthesis, STA and…
  • 3.9
    Cirrus Logic – Austin, TX
    Est. Salary $90k-$134k
    12 days ago 12d
    mixed-signal designers developing ASICs for next generation MEMS based microphones. Participate in all aspects of design from concept… Master's in Electrical Engineering with 10+ years of experience or PhD in Electrical Engineering with 8+ years of experience…
  • 3.6
    Microchip Technology – Lake Forest, CA
    Est. Salary $61k-$84k
    8 days ago 8d
    complex, highly integrated ASICs  - Design documentation and IP generation. Requirements:  - With a minimum of an MS degree… product Wireless group. As a senior member of the team, the designer will be responsible for systems design and implementation tasks…
  • 4.4
    SpaceX – Redmond, WA
    19 days ago 19d
    goal of enabling human life on Mars. SENIORASIC / SoC SYSTEM INTEGRATION ENGINEER RESPONSIBILITIES: You will be responsible… for challenging problems. You will interact with the system engineer team to arrive at the right system-level trade-offs that satisfy…
  • 2.8
    SK Hynix Memory Solutions – San Jose, CA
    Est. Salary $92k-$119k
    16 days ago 16d
    Descriptions: The ASICDesignEngineer will be working on the leading edge SSD controller IP design from architecture to production… support physicaldesign and system level analysis. Qualifications: BS, MS, or PhD in Electrical Engineering with 5-10…
  • 5.0
    CMP.jobs – Austin, TX
    NEW
    line expansion Cirrus logic is looking for a skilled PhysicalDesignEngineer to join its Implementation team. The team is currently… independently and as part of a wider design team. Responsibilities Involved in all aspects of physical implementation from RTL to…
  • 4.0
    Mentor Graphics – Fremont, CA
    Est. Salary $98k-$134k
    19 days ago 19d
    these phases in the physicaldesign flow for large digital ASIC or COT flow SoC (System-on-Chip) designs is required. Experience… exchanging ideas with other application engineers, helping users find solutions to their physicaldesign challenges, and debugging issues…
  • 3.4
    Advanced Micro Devices, Inc. – Austin, TX
    Est. Salary $94k-$128k
    30+ days ago 30d+
    introduction Member of the ASIC Core team and co-leader, will inherit Design Director Team representation if design-director rolls-off… and internal executive communications ASIC RTM recommendations to ACT and resulting ASIC quality and cost Key deliverables…
  • 4.4
    SpaceX – Redmond, WA
    Est. Salary $93k-$131k
    19 days ago 19d
    Mars. SENIORASIC / FPGA VERIFICATION ENGINEER RESPONSIBILITIES: We are looking to hire a Senior Verification Engineer with hands-on… leadership skills. As a Senior verification Engineer youll help define the verification methodology for the complex ASICs and FPGAs. You…
  • 3.6
    Analog Devices – United States
    Est. Salary $79k-$103k
    NEW
    Verilog, and overall ASICdesign flow Solid understanding and experience with mixed signal ICs and designing digital functions… patterns to aid in verification Work with physicaldesignengineers for backend design, floor planning, timing closure and scan…
  • 4.7
    Macropace Technologies – San Jose, CA
    EASY APPLY
    Est. Salary $76k-$106k
    NEW
    PHYSICALDESIGNENGINEER San Jose, CA Fulltime/ Contract Job Description: You will be part of a PhysicalDesign team… and Physical Verification closure of SoC/sub-chips. Desired Skills and Experience: Experience in PhysicalDesign Handled…
  • 3.4
    Micron – Milpitas, CA
    Est. Salary $118k-$155k
    11 days ago 11d
    of these products. You will collaborate with ASICdesigners and other engineering departments including system architecture, hardware… Req. ID: 87277 As a Senior Module DesignEngineer at Micron Technology, Inc., within the Compute and Networking Business Unit…
  • 3.6
    Redolent, Inc – San Jose, CA
    EASY APPLY
    Est. Salary $76k-$105k
    13 days ago 13d
    MATLAB, modeling) Physical Layer Design (USB, HDMI, DDR, MIPI) Digital Design for Mixed Signal ASICs (PLL, Phase-Lock-Loop… disciplines: SoC Design (ASIC integration, Peripherals, Bus Design, DC/PC, LINT, PTSI) RTL Design (Functional/Structural…
Page 1 of 4
Work in HR or Recruiting?