Senior DSP ASIC Design Engineer Jobs | Glassdoor

Senior DSP ASIC Design Engineer Jobs

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  • Approgence – San Jose, CA
    Est. Salary $83k-$110k
    10 days ago 10d
    Job Title : Senior ASIC/ RTL Design Engineer with DSP Job Location : San Diego & San Jose, CA Job Description : This… perform bit-exact simulation. - Modem ASIC Design team is working with physical design engineer to deliver netlist, spec timing constraints…
  • 4.4
    SpaceX – Redmond, WA
    Est. Salary $113k-$151k
    11 days ago 11d
    goal of enabling human life on Mars. SENIOR ASIC ENGINEER RESPONSIBILITIES: Implement ASIC / SoCs / FPGAs for multiple products… Masters degree in engineering or math. ASIC / FPGA / SoC System integration experience. Strong Silicon/ASIC design experience. One…
  • 3.4
    Peraso – United States
    Est. Salary $75k-$101k
    9 days ago 9d
    and one another. As a Senior DSP Engineer, you will work in a fast-paced environment with R&D teams designing architectures and algorithms… Senior DSP Engineer (#006) Posted on December 16, 2016 Description and Responsibilities: Peraso’s DSP engineers develop…
  • 3.0
    Toshiba – San Jose, CA
    Est. Salary $105k-$135k
    30+ days ago 30d+
    development of the SSD Controller ASIC design specification. Will Oversee & Mentor the Flash controller design team in mapping the architecture… , BCH) CPUs, Host interfaces, DSP & high performance protocols. Will oversee SOCs Physical design Investigation of the Emerging…
  • 2.3
    SK Hynix Memory Solutions – United States
    Est. Salary $78k-$110k
    5 days ago 5d
    with Physical Design team to implement design Qualifications: BS, MS or PhD degree in Electrical Engineering or Computer Science… Strong Verilog RTL, SystemC or C/C++, shell scripting skills ECC/DSP experience is highly desirable, but not required Some Perl or…
  • Approgence – Santa Clara, CA
    Est. Salary $99k-$138k
    18 days ago 18d
    Job Title : Senior DSP/RF SW Development Engineer Job Location : Santa Clara, CA Job Description : This is a Full Time… position for a leading chip design and semiconductor company. - Looking for an experienced engineer to drive DSP software/L1 firmware…
  • 3.5
    Ball Aerospace – Boulder, CO
    Est. Salary $85k-$120k
    5 days ago 5d
    achieve a common mission. Senior FPGA and Digital Design Engineer What You'll Do: Design digital hardware including… radiation effects is a plus. Familiarity with ASIC tools, libraries, design flow and fabrication is a plus. Space or military…
  • 2.9
    Avago Technologies – San Diego, CA
    Est. Salary $91k-$120k
    10 days ago 10d
    very hands-on position working with a team of experienced ASIC engineers in a fast past, cutting edge environment that involves a… specifications to working code required. DSP skills, multimedia knowledge, UVM, design automation, and multi-site development experience…
  • 3.2
    Ball Corporation – Boulder, CO
    Est. Salary $66k-$91k
    3 days ago 3d
    mission. Qualifications: Senior FPGA and Digital Design Engineer What You'll Do: * Design digital hardware including FPGA… radiation effects is a plus. * Familiarity with ASIC tools, libraries, design flow and fabrication is a plus. * Space or military…
  • 4.2
    Ball Packaging Europe – Boulder, CO
    Est. Salary $66k-$91k
    6 days ago 6d
    Qualifications: Senior FPGA and Digital Design Engineer What You'll Do: Design digital hardware including… radiation effects is a plus. Familiarity with ASIC tools, libraries, design flow and fabrication is a plus. Space or military…
  • 3.5
    Broadcom – San Diego, CA
    Est. Salary $148k-$188k
    10 days ago 10d
    very hands-on position working with a team of experienced ASIC engineers in a fast past, cutting edge environment that involves a… specifications to working code required. DSP skills, multimedia knowledge, UVM, design automation, and multi-site development experience…
  • 3.4
    Mellanox Technologies – Westborough, MA
    Est. Salary $133k-$177k
    15 days ago 15d
    processors and other computational components such as DSPs, FPGAs and ASICs Excellent written and oral communication skills (English… libraries Executing a complete engineering process, including refining requirements, engineering design of data structures/algorithms…
  • 3.6
    Intel – Santa Clara, CA
    Est. Salary $105k-$142k
    9 days ago 9d
    tools; UVM/OVM verification methods -Synopsys ASIC design tools - VCS simulator, Design Compiler, IC Compiler -Formal verification… corresponding design modifications and optimizations as required to achieve power and performance targets. -Execution of ASIC logic synthesis…
  • Science Referral Network – Tucson, AZ
    8 days ago 8d
    Required Skills for Principal Electrical Engineer (ASIC Design) FPGA ASIC design experience required. Knowledge and experience… We have a PERM position in sunny Tucson, AZ for an ASIC FPGA Designer. There are several positions available at all levels.…
  • 3.6
    Qualcomm – San Diego, CA
    Est. Salary $103k-$134k
    19 days ago 19d
    Job Id E1946679 Job Title Digital RTL Design Engineer, Senior Post Date 03/07/2017 Company - Division… Overview This position involves in-depth understanding of the ASIC design flow from RTL to GDS2 and the challenges posed by advanced…
  • Approgence – Santa Clara, CA
    Est. Salary $91k-$125k
    3 days ago 3d
    SoC Physical Design and RTL Delivery Management for advanced modem Baseband ASIC. - Provide technical support for a team of frontend… : SoC Physical Design Lead Job Location : Santa Clara, CA Job Description : - We are looking for a senior expert in SoC…
  • 3.6
    Qualcomm – San Diego, CA
    Est. Salary $103k-$134k
    17 days ago 17d
    with software teams, algorithm developers, component engineers, ASIC designers and 3rd party vendors will be an integral part of… Job Id E1942871 Job Title Hardware Design Engineer, Senior/Staff Post Date 03/13/2017 Company -…
  • 3.6
    Intel – Santa Clara, CA
    4 days ago 4d
    group. We are looking for a senior expert in SoC architecture and design for advanced modem Baseband ASIC. Provide technical leadership… -10+ years' experience with RTL Logic Design of multi-million gate ASICs/ modem ASIC or wireless AP SoC implementation in complex…
  • 3.6
    Ixia – Beaverton, OR
    3 days ago 3d
    802.11 Experience in design of Test and Measurement equipment Strong working knowledge of MATLAB and DSP design  A little about… Experience with RTL coding for ASICs, FPGAs and bus functional models Proficiency in design flow including items such as lint…
  • 3.6
    Xilinx – San Jose, CA
    Est. Salary $133k-$194k
    14 days ago 14d
    Fundamental experience with EDA tools for FPGA and ASIC designs. Experience with Vivado, ISE or Quartus required (ModelSim is a plus… environment is a plus In-depth knowledge of VHDL or Verilog design for ASIC and FPGA Excellent written and verbal communication skills…
  • 3.6
    Qualcomm – San Diego, CA
    Est. Salary $95k-$128k
    12 days ago 12d
    Minimum Qualifications - ASIC design and verification experience including micro architecture, RTL design and test planning - Embedded… the following skills: - ASIC design and verification experience including micro architecture, RTL design and test planning - Embedded…
  • 3.5
    Broadcom – San Jose, CA
    Est. Salary $86k-$119k
    19 days ago 19d
    thrive in this role include: SERDES-based designs & DSP-hardware designs (EDC, PAM, QPSK, QAM) Implementing networking… implementations This requisition is approved for the Senior Staff Engineer level. At this level, candidates should have BSEE w/…
  • 2.9
    Avago Technologies – San Jose, CA
    Est. Salary $91k-$126k
    21 days ago 21d
    thrive in this role include: SERDES-based designs & DSP-hardware designs (EDC, PAM, QPSK, QAM) Implementing networking… implementations This requisition is approved for the Senior Staff Engineer level. At this level, candidates should have BSEE w/…
  • 4.4
    SpaceX – Redmond, WA
    2 days ago 2d
    high level and working with System Architects, Modem/DSP and BB ASIC engineers to partition functions between HW and SW domains.… electrical engineering with emphasis in RF/Microwave integrated circuits design or analog IC design. Strong circuit design skills,…
  • 3.3
    Cavium, Inc. – San Jose, CA
    Est. Salary $98k-$134k
    19 days ago 19d
    implementation, Vector DSP programming, optimization and debugging is a plus. Experience in working with ASIC design team to guide RTL… detailed specification documents Work closely with ASIC design team to design HW block architecture, verify and validate optimized…
  • 3.3
    NeuroLogica – Danvers, MA
    Est. Salary $59k-$73k
    5 days ago 5d
    wireless chipsets, RFICs and power management ASICs · Drive planning and execution of design verification test, factory test planning… decoupling, low-power supply design and layout of high performance PWBs; Familiarity with modems, DSPs, microprocessors, memories…
  • 3.6
    Qualcomm – San Diego, CA
    Est. Salary $81k-$114k
    5 days ago 5d
    /or DSP design-test and (low-level) debug experience FPGA design and FPGA based emulation Familiarity with VLSI design in HDL… /or DSP design-test and (low-level) debug experience FPGA design and FPGA based emulation Familiarity with VLSI design in HDL…
  • 4.1
    Impinj – Seattle, WA
    Est. Salary $98k-$134k
    27 days ago 27d
    Experience with modem or DSP products. Prior verification experience through the full life cycle of multiple ASIC products. Knowledge… Internet-of-Things. As a Senior Digital Verification Engineer, you will: Collaborate closely with designers, firmware developers,…
  • Approgence – Santa Clara, CA
    17 days ago 17d
    looking for a senior expert in SoC Physical Design and RTL Delivery Management for advanced modem Baseband ASIC. - Provide technical… decision-making skills and the ability to influence across the Baseband ASIC core team as well as other functional teams. - The successful…
  • Approgence – Santa Clara, CA
    Est. Salary $91k-$125k
    16 days ago 16d
    with strong understanding of DSP. - Must be able to collaborate with cross-geo, cross functional design and verification teams. -… Job Title : Senior FPGA/Validation/Verification Engineer (Native Spanish Speaker) Job Location : Santa Clara, CA Job…
  • 3.5
    Raytheon BBN Technologies – Tucson, AZ
    Est. Salary $45k-$64k
    18 days ago 18d
    FPGA/VHDL programming or ASIC support, sustaining and production electronics support, components engineering, and product development… Sophomore, Junior, Senior or Post Graduate level standing pursuing a degree in the following: Electrical Engineering, Electrical Engineering…
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