Staff ASIC Design Verification Engineer Jobs | Glassdoor

Staff ASIC Design Verification Engineer Jobs

70 Jobs
Filters
Filters
  • 3.4
    AMD – Sunnyvale, CA
    Est. Salary $102k-$137k
    Today 9hr
    AMD Sunnyvale for ASIC Physical Design engineer. You will join us as Staff Engineer / Member of Technical Staff. Key Responsibilities… multi-site engineers and managers Qualifications 8+ years' experience with MSEE or MSCE in ASIC Physical Design from RTL…
  • 3.2
    OmniVision Technologies – Santa Clara, CA
    Est. Salary $92k-$128k
    17 days ago 17d
    experience in ASIC design flow: RTL coding, simulation, synthesis, static timing analysis, formality verification, DFT. Extensive… integration and verification. CMOS image sensor array/analog related timing control design and verification. Chip bring-up,…
  • 3.6
    Xilinx – San Jose, CA
    Est. Salary $120k-$152k
    3 days ago 3d
    Wireless FDST Verification group is looking for a Staff Design Verification Engineer to provide technical leadership… full chip verification. The individual will help design, develop and use simulation and/or formal based verification environments…
  • 3.2
    Sony Electronics – San Jose, CA
    Est. Salary $91k-$123k
    20 days ago 20d
    and design. Sony Electronics, a global leader in image sensors, is seeking a staff VLSI/ASIC logic Design Engineer to work… develop and implement solutions Familiarity with ASIC/SoC design/verification methodologies Ability to write detailed and clear…
  • 3.1
    Huawei Technologies – San Diego, CA
    17 days ago 17d
    We are seeking an ASIC Design Engineer to be an important team member in the research, design and verification of SoCs for next… deliver a better future...faster. Senior Staff Engineer - ASIC Design Location: San Diego, CA (R&D) Req #: 8342…
  • 3.3
    Panasonic – Marlborough, MA
    4 days ago 4d
    PDSLM) is seeking a Staff Analog/Mixed-Signal IC design engineer for an exciting opportunity to develop an ASIC within state-of-the-art… Valley. Currently, PRDCA is seeking a Staff Engineer Analog/Mixed Signal ASIC Design What You’ll Get to Do: Architecture…
  • 3.3
    L-3 Communications – Camden, NJ
    Est. Salary $77k-$105k
    5 days ago 5d
    Manager, Engineering (ASIC/FPGA), the Senior Member of Engineering Staff (SMES) will be part of the key ASIC/FPGA design team, responsible… Position Description: Senior ASIC/FPGA Design Engineer L-3 Communications – Communication Systems East (L-3 CS-East)…
  • L3 Technologies – Camden, NJ
    Est. Salary $72k-$96k
    12 days ago 12d
    Manager, Engineering (ASIC/FPGA), the Senior Member of Engineering Staff (SMES) will be part of the key ASIC/FPGA design team, responsible… Job Description !*! Position Description\: Senior ASIC/FPGA Design Engineer L3 Technologies (formerly L-3 Communications) (…
  • 3.4
    SanDisk – Salt Lake City, UT
    Est. Salary $88k-$115k
    9 days ago 9d
    Responsibilities: Design of Verilog HDL for ASIC or FPGA technologies Use of System Verilog for functional verification and debug… Developing Verilog-HDL descriptions of complex logic for ASIC targets. Skills/Experience: The successful candidate…
  • 3.2
    Omnivision Technologies, Inc – Santa Clara, CA
    Est. Salary $92k-$128k
    12 days ago 12d
    experience in ASIC design flow: RTL coding, simulation, synthesis, static timing analysis, formality verification, DFT. Extensive… integration and verification. CMOS image sensor array/analog related timing control design and verification. Chip bring-up,…
  • 3.2
    OmniVision Technologies – Santa Clara, CA
    Est. Salary $117k-$160k
    17 days ago 17d
    test vector generation of ASIC products. Work with test engineering to ensure test vector functionality and stability for mass production… : Participate in module or IP design for SOC project. Full-chip integration and verification Involve in DFT, MBIST and test…
  • 2.8
    SK Hynix – San Jose, CA
    Est. Salary $99k-$135k
    6 days ago 6d
    field of ASIC or NAND flash logic design Experience and expertise in the creation of verification plan Strong hands on experience… automated scripts Experience and expertise in the ASIC design and verification Strong debugging capabilities in RTL/Gate level…
  • 3.9
    Inphi Corporation – Los Altos, CA
    4 days ago 4d
    synthesis, formal verification (LEC), static timing analysis and DFT design implementation/ATPG/verification. The engineer will interface… well with RTL design, test engineering teams to implement highest quality DFT implementation. Will have verification responsibilities…
  • 2.2
    Hynix Semiconductor America – San Jose, CA
    Est. Salary $77k-$106k
    6 days ago 6d
    field of ASIC or NAND flash logic design Experience and expertise in the creation of verification plan Strong hands on experience… automated scripts Experience and expertise in the ASIC design and verification Strong debugging capabilities in RTL/Gate level…
  • 3.0
    Fujitsu – Sunnyvale, CA
    Est. Salary $100k-$138k
    20 days ago 20d
    Physical Design for ASIC using Socionext Advanced Standard Cell technology. The Staff Physical Design Engineer will have opportunities… MSEE preferred. Experience in ASIC/COT design flow. Experience in Physical Design Implementation which includes Floorplan…
  • 2.3
    SK Hynix Memory Solutions – United States
    Est. Salary $78k-$110k
    5 days ago 5d
    perform timing analysis Work with Design Verification and emulation team to validate design Develop functional models for architectural… with Physical Design team to implement design Qualifications: BS, MS or PhD degree in Electrical Engineering or Computer Science…
  • 3.4
    HRL – Malibu, CA
    EASY APPLY
    3 days ago 3d
    Electrical Engineering ESSENTIAL JOB FUNCTIONS: Lead integration, verification, design trade-offs, supervise layout staff, and carry… verify ASIC 2-D stitching, ASIC 3-D stacked hybrids comprising of vastly different PDKs. Interface with front end designers to assist…
  • Fujitsu Network Communications – Sunnyvale, CA
    20 days ago 20d
    Physical Design for ASIC using Socionext Advanced Standard Cell technology. The Staff Physical Design Engineer will have opportunities… are seeking a Staff Physical Design Engineer for our Sunnyvale, CA location. The Staff Physical Design Engineer will provide Physical…
  • 3.4
    stmicroelectronics, inc. – Santa Clara, CA
    6 days ago 6d
    ENGINEER Hardware Design Staff Engineer needed by STMicroelectronics, Inc. in Santa Clara, CA to develop large proprietary SOC… aspects of ASIC FE integration, including top-level development, IPs integration, DFT insertion, timing analysis, handoff checks, formal…
  • 3.9
    Inphi Corporation – Santa Clara, CA
    4 days ago 4d
    Staff Engineer, Analog Design Engineering | Santa Clara, Ca, United States Inphi Background Inphi Corporation, a high-speed… . Experience in EM simulation is a plus. Lab verification and test engineering support. Able to work in multi-disciplinary team…
  • 3.0
    TechUSA – Lowell, MA
    17 days ago 17d
    Interlaken, PCIE) Scripting (Shell, Perl) Staff/ Principal Level FPGA Verification engineer will be based in Lowell and working in… Verilog & UVMTrack record of self-checking complex FPGA (or ASIC) verification test benches Experience with Synopsys VCS or Mentor Questa…
  • 3.2
    Inmata Solutions – San Jose, CA
    Est. Salary $63k-$89k
    22 days ago 22d
    ASIC Verification Engineer Location: Aliso Viejo, CA Description Role & responsibilities: Join a verification team… responsible for the verification of state of the art networking ASIC designs. As part of the verification effort, new and advanced…
  • 2.9
    Microsemi – Sunnyvale, CA
    Est. Salary $112k-$159k
    5 days ago 5d
    other similar tools. * Working knowledge of ASIC design processes (design, verification, implementation, layout) and flows. * Protocol… and experience. * Working knowledge with Design and Verification tools such as Design Compiler, Cadence NC-Sim, waveform viewers…
  • 3.7
    Synaptics – San Jose, CA
    Est. Salary $88k-$121k
    5 days ago 5d
    Responsibilities The IC Design team is searching for a hands-on, team oriented, ASIC design engineer with strong digital design expertise.… system-on-a-chip (SOC) ICs. Work closely with the Design Verification team on functional verification and coverage Work closely with Implementation…
  • 3.5
    Broadcom Corporation – Santa Clara, CA
    Est. Salary $118k-$156k
    3 days ago 3d
    years with MSEE/MSCE in ASIC Physical Design from RTL to GDSII * Strong experience in Physical Design place and route; Floorplanning… * Strong skills in Physical Verification (DRC/LVS/ERC/ANT) with digital and mixed-signal designs * Strong Timing closure skills…
  • 2.4
    Microvision Inc. – Redmond, WA
    Est. Salary $94k-$129k
    16 days ago 16d
    diodes. Perform product and ASIC emulation and prototyping using FPGA devices. Implement design ideas and concepts, including… design robustness.( FPGA/ASIC/Analog functionality) Organize, structure and deliver design documentation packages to document control…
  • 3.5
    Microchip Technology – Chandler, AZ
    6 days ago 6d
    RTL design, design verification, synthesis, STA, floor planning, and power analysis using an industry leading ASIC design flow… achieved. · Work with the design team in overcoming HDL design challenges, achieving verification goals, and assisting with critical…
  • 3.5
    Renesas Electronics America – Santa Clara, CA
    Est. Salary $126k-$164k
    12 days ago 12d
    software • Create and document tests that can be included in ASIC verification process. • Create real-world applications to test SoC… Number 17-0029 Post Date 3/21/2017 Title Sr. Staff Systems Design Engineer City Santa Clara State CA Description Renesas…
  • 3.6
    Ixia – Beaverton, OR
    Today 11hr
    Experience with RTL coding for ASICs, FPGAs and bus functional models * Proficiency in design flow including items such as lint… FPGA Engineer. The list of cutting edge products we develop includes Legitimate Discrete High-Performance Radio Designs for WiFi…
  • 3.9
    Inphi Corporation – Santa Clara, CA
    9 days ago 9d
    seeking to hire Senior Staff Design engineer for primary contribution to innovative, industry leading PHY ASIC development activities… to identify design improvements The successful candidate will be experienced with the IC/ASIC design/verification flow through…
Page 1 of 3
Be the first to get new jobs like these: