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ASIC Design Engineer Jobs in Sunnyvale, CA

470Jobs

  • 4.4
    VeriSilicon Holdings Co., Ltd. – San Jose, CA
    EASY APPLY
    $92k-$124k(Glassdoor est.)
    HOT
    front-end complex RTL design Programming skills in Verilog Must be familiar with all stages of the ASICdesign flow (including… of computer graphics and low-power design techniques a plus Experience of GPU shader design a plus…
  • 3.6
    Infinera – Sunnyvale, CA
    $109k-$141k(Glassdoor est.)
    16 days ago 16d
    impact on internal designs and architecture. Micro-architecture and design of ASIC/FPGA: Includes design documentation, review… 0-2years of experience in ASICDesign. Participation in at least 1 full ASIC cycle as a designer from Arch to Bringup Good…
  • 3.8
    Fortinet – Sunnyvale, CA
    $150k-$195k(Glassdoor est.)
    NEW
    performance ASICdesign from specification to system bring up; · FPGA design experience to verify large scale ASIC · Networking… Responsibilities: · ASIC architecture research, analysis and specification · High performance and high quality ASICdesign from specification…
  • 3.9
    Quanergy – Sunnyvale, CA
    $88k-$115k(Glassdoor est.)
    11 days ago 11d
    Digital ASICDesignEngineer-17040008 Location: Sunnyvale, California, United States Full-time The Digital ASICDesign Engineer… characterize/test the performance of the designedASIC, and work to integrate the design into our LiDAR sensors. A successful…
  • 3.7
    Marvell Technology – Santa Clara, CA
    $89k-$112k(Glassdoor est.)
    NEW
    micro-architecture Implement RTL design in Verilog, Lint check and module level verification Create design documentation, programming… programming guide to software engineers or customers Support verification effort at chip level Support IP integration with SOC…
  • 3.6
    Infinera – Sunnyvale, CA
    $159k-$204k(Glassdoor est.)
    25 days ago 25d
    impact on internal designs and architecture. Micro-architecture and design of ASIC/FPGA: Includes design documentation, review… 7+ years of experience in ASICDesign. Participation in at least 1 full ASIC cycle as a designer from Arch to Bringup Good…
  • 3.7
    Intel Corporation – San Jose, CA
    $94k-$122k(Glassdoor est.)
    9 days ago 9d
    Category: Engineering Primary Location: San Jose, CA US Other Locations: Job Type: Experienced Hire ASIC Design… Design Engineer Job Description Responsibilities: Oversees definition, design, verification, and documentation for SoC System…
  • 3.7
    Qualcomm – San Jose, CA
    $105k-$135k(Glassdoor est.)
    4 days ago 4d
    protocol. The role of an wireless ASICdesignengineer at Qualcomm is the specification, design, verification and implementation… Job Id E1956136 Job Title Wi-Fi ASICDesignEngineer Post Date 10/18/2017 Company Division Qualcomm…
  • 3.8
    winmax – San Jose, CA
    $103k-$143k(Glassdoor est.)
    NEW
    ASIC Verification Engineer/IC DesignEngineer San Jose, CA Full Time Hire Job Description: Our direct client… client is looking for a strong and expert level ASIC Verification Engineer in the area of PCIe SSD Controller verification working…
  • 4.0
    Apple – Santa Clara, CA
    $112k-$156k(Glassdoor est.)
    26 days ago 26d
    ASICDesign Integration Engineer Job Number: 52280683 Santa Clara Valley, California, United States Posted: Oct. 2, 2017… quality design. Key Qualifications This position requires thorough knowledge of the ASICdesign flow, FE and Design verification…
  • 4.0
    Apple – Santa Clara, CA
    $127k-$171k(Glassdoor est.)
    NEW
    ASICDesignEngineer - Fabric/Interconnect Job Number: 113144591 Santa Clara Valley, California, United States Posted:… with 5+ years of work experience in ASICdesign RTL Logic Design in multi-million gate ASICs with Verilog or System Verilog Hands…
  • 4.4
    Google – Mountain View, CA
    $98k-$124k(Glassdoor est.)
    7 days ago 7d
    complex digital design blocks by fully understanding the design specification and interacting with designengineers to identify important… and corner-cases. Debug tests with designengineers to deliver functionally correct design blocks. Close coverage measures to…
  • 4.0
    Cadence Design Systems Inc. – San Jose, CA
    $126k-$169k(Glassdoor est.)
    6 days ago 6d
    technology team responsible for research and development of these ASICengines and how they work as a system to reprogrammably emulate customers… or Computer Engineering, graduate level or compensating experience. Proven success in development of complex ASIC, FPGAs and…
  • 3.9
    Palo Alto Networks – Santa Clara, CA
    HOT
    Opportunities: You will have chance to learn about ASIC/FPGA design, design verification, hardware lab testing through your independently… working with our ASIC/FPGA team which delivers chip for the hardware system. Past projects have ranged from ASIC/FPGA function module…
  • 3.8
    Fortinet – Sunnyvale, CA
    $135k-$175k(Glassdoor est.)
    22 days ago 22d
    performance ASICdesign from specification to system bring up; FPGA design experience to verify large scale ASIC Networking… Responsibilities: ASIC architecture research, analysis and specification High performance and high quality ASICdesign from specification…
  • 4.7
    Macropace Technologies – San Jose, CA
    EASY APPLY
    $83k-$114k(Glassdoor est.)
    8 days ago 8d
    experience with complex ASICdesigns and/or verification Experience in leading a small team of engineers Familiar with System… ASIC Verification Engineer San Jose, CA Full Time Position Job Description: Pre-silicon system verification. This…
  • 3.9
    Palo Alto Networks – Santa Clara, CA
    $78k-$100k(Glassdoor est.)
    HOT
    hardware including Board, FPGA and ASIC. You will be working on our Board Hardware team who designs and tests printed circuit assemblies… involve use of design software and lab equipment. Learning Opportunities: You will participate in the design of new product…
  • 3.9
    Cisco Systems – San Jose, CA
    $105k-$143k(Glassdoor est.)
    NEW
    forwarding was performed in dedicated ASICdesigns. These days we are looking to make those ASICs more general and programmable. P4… traffic management features in ASICs, including queuing, shaping, policing, QOS Familiarity with ASIC abstraction layers Experience…
  • 4.4
    ATR International – Sunnyvale, CA
    $90k-$119k(Glassdoor est.)
    11 days ago 11d
    Information Requisition No.: ATR139876 Position title: Sr. ASICDesignEngineer Location : Sunnyvale, CA Contact Information… Job Description: We are seeking a seasoned DesignEngineer for our ASIC business unit. The primary responsibilities…
  • ASICSoft, Inc. – San Jose, CA
    30+ days ago 30d+
    7-10+ years ASICDesign Strong RTL Design with SystemVerilog Experienced with Synthesis and Timing Closure FPGA Lab…
  • 4.4
    ConnectTel, Inc. – Sunnyvale, CA
    24 days ago 24d
    Our client is looking for Asic Physical Design Place and Route Engineers for its Sunnyvale, CA location. Estimated Contract… Required Skills: Over 6 years experience in ASIC Physical Design from RTL to GDSII. Excellent analytical and problem…
  • 3.6
    Samsung Semiconductor, Inc. – San Jose, CA
    $83k-$114k(Glassdoor est.)
    19 days ago 19d
    JOB TITLE ASIC Verification Engineer Requisition ID DSA31469 OVERVIEW We are looking for an ASIC Verification… chipset company is a primary requirement Strong knowledge with ASIC Simulation Tool & Verification Language: all sign-off simulators…
  • 3.9
    Cohere Technologies, Inc – Santa Clara, CA
    $95k-$128k(Glassdoor est.)
    8 days ago 8d
    position for a Senior FPGA/ASICDesignEngineer in our Santa Clara office. In this position, you will design, implement and test digital… perform the detailed design and verification. This position reports directly to the Director of FPGA/ASICEngineering Required Qualifications…
  • Approgence – San Jose, CA
    $83k-$117k(Glassdoor est.)
    18 days ago 18d
    Job Title : ASIC Physical DesignEngineer Job Location : San Diego & San Jose, CA Job Description : This person will… gate ASICs Working Knowledge of Modem Architecture and HDL languages like verilog to be able to work with logic design team…
  • 4.0
    Apple – Santa Clara, CA
    $127k-$171k(Glassdoor est.)
    26 days ago 26d
    Analog ASICDesignEngineer - CSM Job Number: 52357689 Santa Clara Valley, California, United States Posted: Oct. 4, 2017… subsystem development groups and internal/external ASIC development engineering teams to ensure proper specifications, documentation…
  • 3.6
    Software Galaxy Systems, LLC – Sunnyvale, CA
    $77k-$108k(Glassdoor est.)
    16 days ago 16d
    ASIC Physical Design Place and Route Engineer Location: Sunnyvale, CA 94088 Pay Rate: $60-$90/hour W2 (Depending on Experience… REQUIREMENTS: Over 6 years’ experience in ASIC Physical Design from RTL to GDSII Excellent analytical and problem…
  • 3.6
    Broadcom – San Jose, CA
    $92k-$125k(Glassdoor est.)
    27 days ago 27d
    implementing, and testing high performance communications/networking ASIC products. Candidates with other qualifications will be considered… the frontend digital design flow, and may involve: translating system requirements into engineering specifications defining…
  • 4.1
    Quantum Tech USA – San Jose, CA
    $99k-$131k(Glassdoor est.)
    NEW
    Job Title: Senior / Lead ASICDesignEngineers Location: San Jose, CA Duration : 6-8 months contract Roles & Responsibilities… disciplines: SoC Design (ASIC integration, Peripherals, Bus Design, DC/PC, LINT, PTSI) RTL Design (Functional/Structural…
  • 3.7
    Marvell Technology – Santa Clara, CA
    $89k-$112k(Glassdoor est.)
    5 days ago 5d
    Qualification: A BS, MS or PhD in Electrical or Computer Engineering or similar discipline Experience in behavioral and RTL… circuits. Perform RTL, pre- and post-layout verification of designs on block and system levels using simulation software. Execute…
  • 4.4
    Google – Mountain View, CA
    $106k-$141k(Glassdoor est.)
    24 days ago 24d
    degree in Electrical Engineering or equivalent practical experience. Experience in software design and ASICdesign methodology development… installation/troubleshooting/debugging with vendors. As an ASICDesignEngineer on the chip implementation team, you will be responsible…
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