Job Type
Date Posted
Salary Range
Distance

ASIC Verification Engineer Jobs in Sunnyvale, CA

305Jobs

  • 3.7
    Intel Corporation – San Jose, CA
    $102k-$146k(Glassdoor est.)
    NEW
    Category: Engineering Primary Location: San Jose, CA US Other Locations: Job Type: ASIC-SoC Frontend… Frontend Design and Integration Engineer Job Description As a member of the ASIC Frontend Design and Integration team, you will…
  • 4.4
    Google – Mountain View, CA
    10 days ago 10d
    understanding of ASIC design flows and methodology including RTL, verification, synthesis, STA, formal verification on 28nm and 16nm… Electrical Engineering or equivalent practical experience. 7 years of ASIC design flow experience. Experience with ASIC power analysis…
  • 4.0
    Apple – Santa Clara, CA
    $115k-$157k(Glassdoor est.)
    6 days ago 6d
    Qualifications Advanced knowledge of standard ASIC design and verification flows including RTL design, simulation and testbench… Digital VerificationEngineer Job Number: 50863713 Santa Clara Valley, California, United States Posted: Oct. 19, 2017…
  • 4.0
    Apple – Santa Clara, CA
    $127k-$171k(Glassdoor est.)
    NEW
    Subsystem Engineering groups during engineering specification development and feasibility studies. •Technical management of ASIC suppliers… Establish and review the simulation methodology and verification requirements. - ASIC Development schedules. - Establish design review…
  • 3.6
    Broadcom – Santa Clara, CA
    $106k-$143k(Glassdoor est.)
    NEW
    with design engineers to verify fixes. ○ Write diagnostics for validation of FPGA prototype (pre-tapeout) and ASIC. ○ Replicate… initiatives. As a verificationengineer, your responsibilities will include: ○ Architect block and full-chip verification environments…
  • 2.9
    Avago Technologies – Santa Clara, CA
    $108k-$141k(Glassdoor est.)
    NEW
    with design engineers to verify fixes. ○ Write diagnostics for validation of FPGA prototype (pre-tapeout) and ASIC. ○ Replicate… initiatives. As a verificationengineer, your responsibilities will include: ○ Architect block and full-chip verification environments…
  • 3.7
    Lockheed Martin – Sunnyvale, CA
    $88k-$119k(Glassdoor est.)
    5 days ago 5d
    Digital Processor ASIC/FPGA Designer: The Staff ASIC/FPGA Design Engineer will be working in the Optical Payloads Center of… support foundry backend development activities (ASIC). Develop verification plans and approaches to support development.…
  • Seagate Technology LLC – Fremont, CA
    $96k-$131k(Glassdoor est.)
    20 days ago 20d
    171324 Senior Staff ASIC Design and VerificationEngineer (Open) Seagate delivers advanced digital storage solutions to meet… Experience with advance ASIC design verification methodology such as UVM and VMM flow. Experience with all popular ASIC EDA tools like…
  • 4.1
    Cadence Design Systems – San Jose, CA
    $126k-$169k(Glassdoor est.)
    5 days ago 5d
    technology team responsible for research and development of these ASICengines and how they work as a system to reprogrammably emulate customers… or Computer Engineering, graduate level or compensating experience. Proven success in development of complex ASIC, FPGAs and products…
  • 4.7
    Macropace Technologies – San Jose, CA
    EASY APPLY
    $83k-$114k(Glassdoor est.)
    12 days ago 12d
    full coverage verification plan Experience on Emulation will be an add on. 8+ years of experience with complex ASIC designs and… VerificationEngineer San Jose, CA Full Time Position Job Description: Pre-silicon system verification. This include…
  • 3.6
    Broadcom Corporation – Sunnyvale, CA
    $109k-$141k(Glassdoor est.)
    7 days ago 7d
    seeking an IC design Verificationengineer to work on our next generation 802.11ax Wifi PHY modem ASICVerification You will work on… Cycle Accurate matching, Analog to Digital verification, Radio model verification a plus Experience with silicon bring-up and…
  • 4.7
    Macropace Technologies – Mountain View, CA
    EASY APPLY
    $83k-$114k(Glassdoor est.)
    23 days ago 23d
    Makefiles, Perl scripting a must Chip/full system level ASICVerification skills, and debug skills a must. Debug using waveforms… System Level Verification Mountain View, CA Full Time Position Job Description: Verilog and C/C++ coding a must…
  • 4.7
    Macropace Technologies – Mountain View, CA
    EASY APPLY
    $83k-$114k(Glassdoor est.)
    19 days ago 19d
    Makefiles, Perl scripting a must Chip/full system level ASICVerification skills, and debug skills a must. Debug using waveforms… System Level Verification Mountain View, CA Full Time Position Job Description: Verilog and C/C++ coding a must…
  • 3.1
    Fujitsu – Sunnyvale, CA
    $105k-$135k(Glassdoor est.)
    28 days ago 28d
    , ACE and AHB ASIC Design Verification experience in block level as well as subsystem level verification using UVM, gate level… .com/en/ We are seeking a seasoned Design Engineer for our ASIC business unit. The primary responsibilities include…
  • 3.0
    Seagate Technology – Fremont, CA
    $113k-$150k(Glassdoor est.)
    23 days ago 23d
    171324 Senior Staff ASIC Design and VerificationEngineer (Open) Seagate delivers advanced digital storage solutions to meet… Experience with advance ASIC design verification methodology such as UVM and VMM flow. Experience with all popular ASIC EDA tools like…
  • 4.2
    Varite – San Jose, CA
    NEW
    Minimum Requirements: 1. BSEE 2. 10+ yrs exp 3. ASIC Design Verification Exp. Desired Skills: 1. UVM, VMM 2. C++,… Engineer-Consultant III(US) Req I D CS-JP00052082 Rate Primary Skills Description 7 years of experience…
  • 4.1
    TEEMA Solutions Group – Sunnyvale, CA
    22 days ago 22d
    Category: Engineering | Job Type: Contract Apply Now! ASIC Physical Design Place and Route Engineer KEY RESPONSIBILITIES… website at www.teemagroup.com | ASIC Physical Design Place and Route Engineer x5 Sunnyvale, California, United States…
  • 5.0
    Tarana Wireless – Santa Clara, CA
    EASY APPLY
    $106k-$144k(Glassdoor est.)
    13 days ago 13d
    interference cancellation, in FPGA or ASICs. Implementation of DSP algorithms in FPGA or ASIC, including: digital filtering, resampling… years full­time working experience in logic designs for FPGA or ASIC. Knowledge, Skills and Abilities: Extensive high­speed…
  • 4.4
    Google – Mountain View, CA
    $106k-$146k(Glassdoor est.)
    17 days ago 17d
    formal verification of design properties of complex ASIC designs. You must collaborate closely with design and verification engineers… define and improve design and verification methodologies that allow you to achieve formal verification closure. This is a central…
  • 3.7
    Intel – San Jose, CA
    $94k-$122k(Glassdoor est.)
    13 days ago 13d
    Description Responsibilities: Oversees definition, design, verification, and documentation for SoC System on a Chip development.… teams. Strong understanding of hardware design, design verification, timing analysis, clock domain crossing, and lint. Proficient…
  • 2.8
    SK Hynix Memory Solutions – San Jose, CA
    $97k-$132k(Glassdoor est.)
    30+ days ago 30d+
    design engineers to identify important verification scenarios. Create a constrained-random verification environment using SystemVerilog… with design engineers to deliver functionally correct design blocks. Close coverage measures to identify verification holes and…
  • 4.3
    Zensa – Mountain View, CA
    $83k-$114k(Glassdoor est.)
    15 days ago 15d
    Makefiles, Perl scripting a must Chip/full system level ASICVerification skills, and debug skills a must Debug using waveforms… VerificationEngineer - System Level Location: Mountain View, CA Duration: 6-12 Months Skill set: Verilog and…
  • 3.6
    Broadcom – Sunnyvale, CA
    $109k-$141k(Glassdoor est.)
    NEW
    Knowledge of Verilog/VHDL languages, RTL design/verification, and of ASIC design methodology Experience in one or more of… designers you will help realize complex, highly integrated ASICs. Desired Skills and Qualifications: Typically a BS degree…
  • 4.4
    ATR International – Sunnyvale, CA
    $90k-$119k(Glassdoor est.)
    14 days ago 14d
    , ACE and AHB -ASIC Design Verification experience in block level as well as subsystem level verification using UVM, gate level… Information Requisition No.: ATR139876 Position title: Sr. ASIC Design Engineer Location : Sunnyvale, CA Contact Information…
  • 4.3
    Zensa – Mountain View, CA
    $82k-$106k(Glassdoor est.)
    15 days ago 15d
    5+ years solid ASICverification experience (not design & verification, but strictly verification) 2+ years of solid UVM… Title- Design verificationengineer Location – Redmond, WA Duration – Long Term, 12-18 months Required Skills…
  • 2.8
    Microsemi – Sunnyvale, CA
    $102k-$139k(Glassdoor est.)
    24 days ago 24d
    using UPF flow BSEE (MSEE preferred) 7+ years of ASIC/SoC verification experience Excellent scripting and programming skills… knowledge with Verification tools such as Cadence NC-Sim, waveform viewers, and other similar tools. Working knowledge of ASIC/SoC design…
  • 3.8
    Xilinx – San Jose, CA
    $125k-$157k(Glassdoor est.)
    21 days ago 21d
    Wireless FDST Verification group is looking for a Staff Design VerificationEngineer to provide technical leadership… PCIe verification is a plus. Verification experience in full chip verification is a plus. Familiarity with verification management…
  • 3.6
    Samsung Semiconductor, Inc. – San Jose, CA
    12 days ago 12d
    feasibility, FPGA prototyping and ASIC design Supervise verification contractors and oversee the verification flow Supervise back-end… prototyping and design flow Experience in large-scale system verification and debug Excellent documentation and communication skills…
  • 4.4
    Google – Mountain View, CA
    $106k-$141k(Glassdoor est.)
    28 days ago 28d
    Electrical Engineering Hands on experience and a solid understanding of ASIC DFT, synthesis, simulation and verification flow.… installation/troubleshooting/debugging with vendors. As an ASIC Design Engineer on the chip implementation team, you will be responsible…
  • 4.1
    Cadence Design Systems – San Jose, CA
    $115k-$174k(Glassdoor est.)
    NEW
    RTL, such as Verilog, SystemVerilog, or VHDL. Knowledge of ASIC design and methodology. Good communication skills. We're… maintain verification solutions for our customers. Candidates should have the following: Expertise in formal verification algorithms…
Page 3 of 11
Work in HR or Recruiting?