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Senior ASIC Layout Design Engineer Jobs in Sunnyvale, CA

16 Jobs

  • 3.5
    Advanced Micro Devices, Inc. – Sunnyvale, CA
    $90k-$134k(Glassdoor est.)
    14 days ago 14d
    core designs; perform electronic designengineering & design of GMI interface design. PMTS ASIC/ LayoutDesignEngineer CA1517… lead the IR/EM function. SeniorASIC/LayoutDesignEngineer CA1817: Responsible for physical design of next generation GPUs and…
  • 3.5
    Advanced Micro Devices, Inc. – Sunnyvale, CA
    $90k-$134k(Glassdoor est.)
    15 days ago 15d
    core designs; perform electronic designengineering & design of GMI interface design. PMTS ASIC/ LayoutDesignEngineer CA1517… lead the IR/EM function. SeniorASIC/LayoutDesignEngineer CA1817: Responsible for physical design of next generation GPUs and…
  • 4.0
    Nokia – Sunnyvale, CA
    $118k-$149k(Glassdoor est.)
    HOT
    General Purpose: Works in seniorengineering role in product, system or technology program in SW/HW/System Design or Integration & Verification… components Custom IC layout, in 130nm SOI or deep submicron CMOS at and below 65 nm node Experience in module design preferred (Experience…
  • 3.5
    Advanced Micro Devices, Inc. – Sunnyvale, CA
    $90k-$134k(Glassdoor est.)
    14 days ago 14d
    core designs; perform electronic designengineering & design of GMI interface design. PMTS ASIC/ LayoutDesignEngineer CA1517… lead the IR/EM function. SeniorASIC/LayoutDesignEngineer CA1817: Responsible for physical design of next generation GPUs and…
  • 3.2
    Rambus – Sunnyvale, CA
    $73k-$98k(Glassdoor est.)
    7 days ago 7d
    collaborate with the industry, partnering with leading ASIC and SoC designers, foundries, IP developers, EDA companies and validation… collaborate with the industry, partnering with leading ASIC and SoC designers, foundries, IP developers, EDA companies and validation…
  • 3.2
    Finisar – Sunnyvale, CA
    NEW
    DUTIES & RESPONSIBILITIES: This is a seniorengineer position responsible for designing and developing high speed fiber optics… mechanical, RF design, assembly process, test engineering, and product engineering teams. Responsible for the concept design, EVT, and…
  • 3.8
    Palo Alto Networks – Santa Clara, CA
    $78k-$100k(Glassdoor est.)
    20 days ago 20d
    hardware including Board, FPGA and ASIC. You will be working on our Board Hardware team who designs and tests printed circuit assemblies… Manage and review PCB layout Learn about the complete hardware design cycle including schematic, layout, and test Skills…
  • 3.2
    Rambus – Sunnyvale, CA
    $73k-$99k(Glassdoor est.)
    7 days ago 7d
    collaborate with the industry, partnering with leading ASIC and SoC designers, foundries, IP developers, EDA companies and validation… collaborate with the industry, partnering with leading ASIC and SoC designers, foundries, IP developers, EDA companies and validation…
  • 3.2
    Finisar – Sunnyvale, CA
    4 days ago 4d
    DUTIES & RESPONSIBILITIES: This is a seniorengineer position responsible for designing and developing high speed fiber optics… mechanical, RF design, assembly process, test engineering, and product engineering teams. Responsible for the concept design, EVT, and…
  • 3.2
    Finisar – Sunnyvale, CA
    NEW
    DUTIES & RESPONSIBILITIES: This is a seniorengineer position responsible for designing and developing high speed fiber optics… mechanical, RF design, assembly process, test engineering, and product engineering teams. Responsible for the concept design, EVT, and…
  • 3.6
    Dialog Semiconductor – Campbell, CA
    $97k-$131k(Glassdoor est.)
    5 days ago 5d
    and post layout verification. Collaboration with analog engineers and test engineers on analog testability design and debugging… continued growth, we seek a Senior Digital DesignEngineer. The role Working in the Digital Design - Power Conversion Business…
  • 4.4
    Quantenna Communications – Fremont, CA
    $121k-$163k(Glassdoor est.)
    NEW
    HW engineers and cross functional teams (ASIC and SW). Feedback customers’ inputs to product management and engineering to develop… leading Taiwan ODMs. Reviewing customers’ schematics and layoutdesign. Analyze and resolve RF related hardware issues. Document…
  • 4.4
    NVIDIA – Santa Clara, CA
    $120k-$163k(Glassdoor est.)
    19 days ago 19d
    generation ASIC core power delivery design Drive the next generation HBM (hig—bandwidth memory) interface design Work closely… closely with Architecture, ASIC, Mixed Signal, Package, and PCB Design teams to design and ensure link performance meets expectation…
  • 3.9
    ASML – San Jose, CA
    $76k-$106k(Glassdoor est.)
    13 days ago 13d
    module level Analog and mixed signal ASICdesign and tapeout Analog and mixed signal ASIC PCB level integration Education… signal circuit design and circuit simulation in both board level and IC level, print circuit board (PCB) layout, PCB prototyping…
  • 4.2
    ASIC North, Inc. – San Jose, CA
    30+ days ago 30d+
    complementing customers existing design teams, and providing engineering staff as needed. In addition, ASIC North develops and provides… Manager at ASIC NorthWilliston, Vermont Industry Semiconductors Employment type Full-time Experience Mid-Senior level…
  • 3.7
    MediaTek – San Jose, CA
    $78k-$104k(Glassdoor est.)
    14 days ago 14d
    for TCAM and SRAM memory design for high performance data center switches and network ASICs. Design and implement a high performance… coordinate layout activities Knowledge of transistor level STA tools such as Nanotime Ability to come up with design verification…
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