Senior ASIC Layout Design Engineer Jobs in Sunnyvale, CA | Glassdoor

Senior ASIC Layout Design Engineer Jobs in Sunnyvale, CA

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  • 4.3
    NVIDIA – Santa Clara, CA
    17 days ago 17d
    are now looking for a Senior ASIC Power Engineer: In this role you will be responsible for designing and implementing the chip… products. As a senior team member, you will collaborate closely with Architecture, Software, ASIC, VLSI, DFT, Layout, and Product…
  • 2.7
    Theranos – Palo Alto, CA
    Est. Salary $106k-$152k
    13 days ago 13d
    Electrical Engineering (BSEE) or MSEE (preferred) with 8+ years of industry experience., Must have proven design and development… expertise that are preferred include: Wireless communications, FPGA, ASIC, and signal processing., Experience using a digital simulation…
  • 3.9
    Dialog Semiconductor, Inc. – Santa Clara, CA
    Est. Salary $86k-$117k
    5 days ago 5d
    and post layout verification. Develop test vectors for production test. Instigate review meetings with design engineers. Perform… POSITIION: Senior Digital Design Engineer WORKSITE: 2560 Mission College Blvd., Suite 110, Santa Clara, CA 95054 United States…
  • GigPeak – San Jose, CA
    EASY APPLY
    Est. Salary $106k-$155k
    28 days ago 28d
    Senior ASIC Design Engineer (Job Code WL) REPORTS TO: Director of ASIC Engineering LOCATION: San Jose, CA CLASSIFICATION:… currently seeking a Senior ASIC Design Engineer. Essential Duties and Responsibilities Management of ASIC design development Meet…
  • 3.2
    International Rectifier – Milpitas, CA
    Est. Salary $111k-$146k
    4 days ago 4d
    specifications Design and layout of evaluation boards Perform test characterization of RFIC Drive system engineering engagement… Senior RF Design Engineer At a glance Do you love to create with a passion for Engineering? If you love bringing brilliant…
  • 3.8
    Infineon Technologies – Milpitas, CA
    Est. Salary $109k-$141k
    7 days ago 7d
    specifications Design and layout of evaluation boards Perform test characterization of RFIC Drive system engineering engagement… Senior RF Design Engineer At a glance Do you love to create with a passion for Engineering? If you love bringing brilliant…
  • 4.2
    Inphi Corporation – Santa Clara, CA
    Est. Salary $107k-$142k
    19 days ago 19d
    plus. In addition, the engineer will perform the following ASIC design tasks: Block level physical design and timing closure Static… Minimum 7 years experience and MSEE Must understand chip layout/physical design concepts, methodologies and flows (i.e. floorplanning…
  • 3.8
    Nokia – Sunnyvale, CA
    27 days ago 27d
    General Purpose: Works in senior engineering role in product, system or technology program in SW/HW/System Design or Integration & Verification… • Custom IC layout, in 130nm SOI or deep submicron CMOS at and below 65 nm node • Experience in module design preferred (Experience…
  • 3.4
    Cavium, Inc. – San Jose, CA
    Est. Salary $138k-$188k
    24 days ago 24d
    Noise Analysis for ASICs on 28nm and below technology nodes; Work on Logical Equivalency between RTL and Layout at block and top… Cavium, Inc. seeks Senior Lead Physical Design Engineers (multiple openings) to implement physical design (VLSI) for large high-speed…
  • 4.1
    Cadence Design Systems – San Jose, CA
    Est. Salary $89k-$125k
    4 days ago 4d
    processing ASICs and FPGAs, and is interested in establishing SI/PI system budgets and implementing the advanced design validation… coding, and FEC algorithms. Working knowledge of PCB design and layout, as it impacts signal and power integrity. Working knowledge…
  • 3.7
    Intel – Santa Clara, CA
    10 days ago 10d
    package implications of the silicon design decisions.Preferred Skills:Experience with ASIC based designsExperience implementing… multidimensional designs involving the layout of complex integrated circuits. Performs all aspects of the SoC physical design flow: synthesis…
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