Senior DSP ASIC Design Engineer Jobs in Sunnyvale, CA | Glassdoor

Senior DSP ASIC Design Engineer Jobs in Sunnyvale, CA

10 Jobs
Filters
Filters
  • 3.6
    Intel – Santa Clara, CA
    Est. Salary $105k-$142k
    10 days ago 10d
    tools; UVM/OVM verification methods -Synopsys ASIC design tools - VCS simulator, Design Compiler, IC Compiler -Formal verification… corresponding design modifications and optimizations as required to achieve power and performance targets. -Execution of ASIC logic synthesis…
  • 3.0
    Toshiba – San Jose, CA
    Est. Salary $105k-$135k
    30+ days ago 30d+
    development of the SSD Controller ASIC design specification. Will Oversee & Mentor the Flash controller design team in mapping the architecture… , BCH) CPUs, Host interfaces, DSP & high performance protocols. Will oversee SOCs Physical design Investigation of the Emerging…
  • Approgence – Santa Clara, CA
    Est. Salary $91k-$125k
    4 days ago 4d
    SoC Physical Design and RTL Delivery Management for advanced modem Baseband ASIC. - Provide technical support for a team of frontend… : SoC Physical Design Lead Job Location : Santa Clara, CA Job Description : - We are looking for a senior expert in SoC…
  • 3.5
    Broadcom – San Jose, CA
    Est. Salary $86k-$119k
    20 days ago 20d
    thrive in this role include: SERDES-based designs & DSP-hardware designs (EDC, PAM, QPSK, QAM) Implementing networking… implementations This requisition is approved for the Senior Staff Engineer level. At this level, candidates should have BSEE w/…
  • 2.9
    Avago Technologies – San Jose, CA
    Est. Salary $91k-$126k
    21 days ago 21d
    thrive in this role include: SERDES-based designs & DSP-hardware designs (EDC, PAM, QPSK, QAM) Implementing networking… implementations This requisition is approved for the Senior Staff Engineer level. At this level, candidates should have BSEE w/…
  • 3.6
    Intel – Santa Clara, CA
    5 days ago 5d
    group. We are looking for a senior expert in SoC architecture and design for advanced modem Baseband ASIC. Provide technical leadership… -10+ years' experience with RTL Logic Design of multi-million gate ASICs/ modem ASIC or wireless AP SoC implementation in complex…
  • 3.3
    Cavium, Inc. – San Jose, CA
    Est. Salary $98k-$134k
    19 days ago 19d
    implementation, Vector DSP programming, optimization and debugging is a plus. Experience in working with ASIC design team to guide RTL… detailed specification documents Work closely with ASIC design team to design HW block architecture, verify and validate optimized…
  • 3.6
    Xilinx – San Jose, CA
    Est. Salary $133k-$194k
    14 days ago 14d
    Fundamental experience with EDA tools for FPGA and ASIC designs. Experience with Vivado, ISE or Quartus required (ModelSim is a plus… environment is a plus In-depth knowledge of VHDL or Verilog design for ASIC and FPGA Excellent written and verbal communication skills…
  • 3.0
    Toshiba – San Jose, CA
    Est. Salary $95k-$167k
    30+ days ago 30d+
    PCIe SSD technologies prior to design. Will drive the development of the SSD Controller ASIC design specification. Will Oversee &… ) CPUs, Host interfaces, DSP & high performance protocols. Will oversee Flash and SOC Physical design Investigation of the Emerging…
  • 3.7
    Cavium – San Jose, CA
    Est. Salary $95k-$132k
    30+ days ago 30d+
    implementation, Vector DSP programming, optimization and debugging is a plus. * Experience in working with ASIC design team to guide… detailed specification documents * Work closely with ASIC design team to design HW block architecture, verify and validate optimized…
Page 1 of 1
Be the first to get new jobs like these: