Management was good, very understanding and reason I continued working there.
internal politics, improper funding for company growth.
Interviewed for FPGA Engineer. Had a practical test and then technical round.
Practical test was to write a VHDL code to divide a 160MHz clock to 40MHz, write a testbench and show the results. Have to use Xilinx ISE for coding and ModelSim for simulation.
Technical round had questions from digital design and hardware design in general.
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