Salary: VLSI ASIC Design Verification Engineer in San Jose, CA | Glassdoor

VLSI ASIC Design Verification Engineer Salaries in San Jose, CA

1 Salaries
National Avg
$95,432*
Min
Max
$85k
$112k
San Jose, CA Area Avg
$93,935*
Min
Max
$83k
$110k
Your Market Worth
$XX,XXX
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Recent Salary Reports

Below are the most recent VLSI ASIC Design Verification Engineer salary reports. Employer name has been removed to protect anonymity.

$140,000
per year
An ASIC Design Verification Engineer reported making $140,000 per year
Job Highlights
10+ years experience
Full-time
 
1001 to 5000 employees
Company - Private
$93,000
per year
An ASIC Design Verification Engineer reported making $93,000 per year
Additional Pay
$4k cash bonus
$6k stock bonus
Job Highlights
1-2 years experience
Full-time
 
5001 to 10000 employees
Company - Public
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