Profit Sharing, Commission Sharing, Tips have not been reported for this role.
How much does a ASIC Design Verification Engineer at Marvell Technology make in San Jose, CA? The typical salary for a Marvell Technology San Jose ASIC Design Verification Engineer ranges from $77,858-$94,533, with an average salary of $86,905. Salary estimates based on 26 salary report(s) submitted anonymously to Glassdoor by Marvell Technology ASIC Design Verification Engineer employees in San Jose, CA or estimated based upon statistical methods.
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