Cash Bonus, Stock Bonus, Profit Sharing, Commission Sharing, Tips have not been reported for this role.
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How much does a ASIC Design Verification Engineer at SmartPlay make in Austin, TX? The typical salary for a SmartPlay Austin ASIC Design Verification Engineer ranges from $84,231-$108,658, with an average salary of $94,534. Salary estimates based on 11 salary report(s) submitted anonymously to Glassdoor by SmartPlay ASIC Design Verification Engineer employees in Austin, TX or estimated based upon statistical methods.
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