NetLogic Microsystems Design Engineer interview questions

A small group, so I had a series of 45 minute one-on-one interviews with four technical team members and the manager. Questions regarding past experience, and also technical questions on subjects such as RTL coding of state machines and timing analysis principles, principle of CPU pipelining and stalls. A friendly team, fairly informal and comfortable. The process started with a brief phone screen, covering resume experience. Also need to know about blocking versus non-blocking assignments in verilog RTL code. Follow-up response to interview took about 2 weeks, I inquired by email and received response I was not selected.