Latch-up is a condition in which the parasitic components give rise to the Establishment of low resistance conducting path between VDD and VSS . Latch-up may be induced by glitches on the supply rails or by incident radiation. A byproduct of the Bulk CMOS structure is a pair of parasitic bipolar transistors. The collector of each BJT is connected to the base of the other transistor in a positive feedback structure. A phenomenon called latchup can occur when (1) both BJT's conduct, creating a low resistance path between Vdd and GND and (2) the product of the gains of the two transistors in the feedback loop, b1 x b2, is greater than one. The result of latchup is at the minimum a circuit malfunction, and in the worst case, the destruction of the device due to electrical overstress (EOS).