I was told the next round, post the recruiter call was going to be with the hiring manager. It ended up being someone else on the team, and they were 15 minutes late and rushed through questions. They were a bit inconsiderate and overall was not pleasant.
Other Design Verification Engineer Interview Reviews for Meta
Average. Focus on basics of sv and uvm. Understanding of uvm config db and other benefits of uvm is needed. Sv constraints is v important. All the comp of tb specifically scoreboard is vital
HR guidance to the process was on top. There was a long delay of 3 weeks+ to schedule forst round itself
first Followed by 2 edcoding tech rounds initially.
Following which there would be loop interviews. Followed by HR round at the end.
Interview questions [1]
Question 1
Sv constraints on memory block and region. GLS questions on debug flow.
