I applied online. I interviewed at Cadence Design Systems (San Jose, CA)
Interview
Phone interview was scheduled through Email, asked basic Verilog question. Then I was called for an onsite. Received Offer after 2 days.
Important topics:
Writing Synthesizable Code
Understanding ASIC flow.
Assertions.
How do to debug a design.
Interview questions [2]
Question 1
Difference between Blocking and non blocking assignment stmts.