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      Synopsys

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      ASIC DIGITAL DESIGN ENGINEER II Interview

      Sep 19, 2022
      Anonymous employee
      Toronto, ON

      Other ASIC DIGITAL DESIGN ENGINEER II Interview Reviews for Synopsys

      ASIC Digital Design Engineer, II Interview

      Oct 19, 2023
      Anonymous Interview Candidate
      Mississauga, ON
      No offer
      Accepted offer
      Positive experience
      Difficult interview

      Application

      I applied through an employee referral. The process took 1 week. I interviewed at Synopsys (Toronto, ON) in Apr 2022

      Interview

      3 round of interviews. basic knowledge. Some code test. Some system knowledge test. It should depends of your year of experience and the previous job experience. They may ask you about your preference of job duty. Get an offer finally.

      Interview questions [1]

      Question 1

      Some code test. Some system knowledge test.
      Answer question
      Negative experience
      Average interview

      Application

      I applied online. The process took 3 weeks. I interviewed at Synopsys (Mississauga, ON) in Sep 2023

      Interview

      Passed the initial interview, then was asked to do 4 more interviews, Was asked to accommodate to their schedule and interview at 8am for 3 days straight, with 2 interviews in one day. Then on the final interview, interview was cut short and interviewer said I was too junior for role.

      Interview questions [1]

      Question 1

      Lots of questions about pmos and nmos (how to build nand gates, inverters), etc, how a pll works, how different things affect the output, transmission lines (parasitics, series vs parallel etc), flip flops, latches, op amps (designing lots of different op amps and discussing their rules)
      Answer question
      1

      ASIC Digital Design Engineer, II Interview

      Dec 29, 2022
      Anonymous employee
      Porto, Oporto
      Accepted offer
      Positive experience
      Average interview

      Application

      I applied online. I interviewed at Synopsys (Porto, Oporto) in Aug 2022

      Interview

      3 interviews, all of them 90% technical, with 2 different engineers from Security IP team and your future boss. First interview was with my future boss, with an overall talk about how the team works, which are the current products, where will I fit the most if everything goes well, background, my personal desires, etc. Then switch to technical questions, more related to key concepts of ASIC Design in general (not particular products or code). Power aspects, synthesis, design flow, CDC. The other 2 interviews were 100% techincal, with more specific questions about Digital Design modules/architectures: FIFOs, memories, datapath, together with Cybersecurity protocols basics

      Interview questions [4]

      Question 1

      Design FIFO module control for synchronous write and asynchronous read with given constraints (full, empty, etc)
      Answer question

      Question 2

      How can I estimate a new IP complexity and area without having any specific details yet?
      Answer question

      Question 3

      Basic Verilog code questions, such as latch inferences, correct assignations (not mixing blocking/non blocking), FSM, etc
      Answer question

      Question 4

      CDC and related concepts. Clock main issues, metastability, glitching, etc, and the possible solutions
      Answer question