FPGA Engineer Intern applicants have rated the interview process at Optiver with 3.2 out of 5 (where 5 is the highest level of difficulty) and assessed their interview experience as 40% positive. To compare, the company-average is 49.2% positive. This is according to Glassdoor user ratings.
Candidates applying for FPGA Engineer Intern roles take an average of 30 days to get hired, when considering 5 user submitted interviews for this role. To compare, the hiring process at Optiver overall takes an average of 21 days.
Common stages of the interview process at Optiver as a FPGA Engineer Intern according to 5 Glassdoor interviews include:
Skills test: 100%
Here are the most commonly searched roles for interview reports -
phone screen then technical then another technical then superday at the end so basically 4 rounds of interview for the job. phone screen not too bad but you get re resume screened after
Interview questions [1]
Question 1
why optiver, describe most recent experience and whats the thing ur most proud of in that exp, did u apply to any other hfts, and then a technical was system design with content addressable memory using hash keys
Received an invitation to complete an online assessment the day after applying. The assessment was 30 questions and you were given 24 hours to finish it once started. The assessment consisted of some multiple choice, some free response, and 1 leet code style coding question.
Interview questions [1]
Question 1
The 1 leet code style question was laughably easy. The rest of the assessment consisted of various questions on HDLs, boolean algebra/minimization, digital design, and time complexity.
I applied online. I interviewed at Optiver (Chicago, IL)
Interview
after applying for 2 or 3 days, i got a test. I need to finish it in 24 hours in a week. The test include basic digital design question and some FPGA question. Also a easy coding question.
Interview questions [1]
Question 1
For the first test, you need to know the basic knowledge of digital design and some knowledge about system verilog and lookup table