ASIC Design Verification Engineer applicants have rated the interview process at Marvell Technology with 4 out of 5 (where 5 is the highest level of difficulty) and assessed their interview experience as 50% positive. To compare, the company-average is 58.9% positive. This is according to Glassdoor user ratings.
Candidates applying for ASIC Design Verification Engineer roles take an average of 7 days to get hired, when considering 2 user submitted interviews for this role. To compare, the hiring process at Marvell Technology overall takes an average of 20 days.
Common stages of the interview process at Marvell Technology as a ASIC Design Verification Engineer according to 2 Glassdoor interviews include:
Presentation: 50%
Personality test: 25%
One on one interview: 25%
Here are the most commonly searched roles for interview reports -
I applied in-person. The process took 1 week. I interviewed at Marvell Technology in Jan 2022
Interview
The interview process was flawless and easy.
The interview was arranged as per the mutual availability of the interviewer and the candidate, and feedback was also provided soon.
Whole process was completed within a week.
Interview questions [1]
Question 1
Current project architecture and role.
SV and UVM related.
SV constraint, coverage, assertions.
UVM architecture and flow.
Verification strategy related.
I applied through other source. I interviewed at Marvell Technology in Oct 2019
Interview
Got the interview opportunity through a career fair. The interview was scheduled in three days. Two phone interview followed by a onsite interview. First phone interview started as technical No HR conversation in the beginning.
Interview questions [1]
Question 1
virtual memory
standard libraries in C
how to build a cache
how will you move data in cache
what is recursion
linked lists,
binary tree,
flat architecture,
how a CPU would work