Xilinx Interview Questions | Glassdoor

Xilinx Interview Questions

Interviews at Xilinx

206 Interview Reviews

Experience

Experience
64%
23%
13%

Getting an Interview

Getting an Interview
46%
19%
16%
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6
3
1

Difficulty

3.0
Average

Difficulty

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  1. Featured Interview

     

    Software Engineer Interview

    Anonymous Employee
    Accepted Offer
    Positive Experience
    Average Interview

    Interview

    The interview process moved very quickly and involved a technical phone screen followed by 5 technical/behavioral interviews with the team. Technical questions were a mix of coding and seeing how familiar you are with certain concepts.

    Interview Questions

    • I won't disclose specific questions out of respect, but freshen up on scheduling, process synchronization, inter-process communication, memory management, interrupt handling, DMAs, OS and RTOS concepts, and anything else that might be relevant to the position.   2 Answers
    • For behavioral questions, they're mostly looking to see how you solve problems, your own work history, and how interested you are in the position.   1 Answer

  2.  

    Intern Interview

    Anonymous Employee
    Accepted Offer
    Positive Experience
    Difficult Interview

    Interview

    2 phone interviews one day after the other which were both technical and behavioral in nature. Second was a little more technical than the first. Problems were done on google docs

    Interview Questions

    • Some of the easier ones were general bit manipulation problems   Answer Question
  3.  

    Software Engineer() Interview

    Anonymous Interview Candidate in Tempe, AZ
    No Offer
    Positive Experience
    Average Interview

    Application

    I applied through a recruiter. I interviewed at Xilinx (Tempe, AZ).

    Interview

    I got this opportunity by directly contacting the manager I happened to connect with on Linked in. This was a 45 min interview mainly based on my projects in the resume and some coding questions . 2 coding questions . I was provided with a online editor for the same .

    Interview Questions


  4. Helpful (1)  

    Verification Design Engineer Interview

    Anonymous Interview Candidate in San Jose, CA
    Declined Offer
    Negative Experience
    Average Interview

    Application

    I applied online. The process took 3 weeks. I interviewed at Xilinx (San Jose, CA) in September 2019.

    Interview

    I applied on the website, did a phone interview, then did an onsite. They told me they moved fast and to expect my results soon. I thought I didn't do well, so when they didn't email me for a week, I just assumed I didn't pass.

    3 weeks later, out of the blue, they called me saying that wanted to offer me the position. They hesitated to give me exact details, saying they wanted to know if I would accept on the spot. They were very pushy about this, and came off very unprofessional. When I couldn't accept on the spot, they seemed really impatient and didn't want to give me much time to think about it. I ended up not taking their offer.

    Interview Questions

    • for the onsite, 45 min each of the following:

      - introductory, asking about my resume, background, etc.
      - OOP concepts and questions
      - digital design/logic puzzle questions
      - introductory signals and systems
      - clock domain crossing questions
      - what cases you need to verify a given design   Answer Question

  5.  

    Design Engineer Interview

    Anonymous Interview Candidate in San Jose, CA
    No Offer
    Positive Experience
    Average Interview

    Application

    I applied through an employee referral. The process took 5 days. I interviewed at Xilinx (San Jose, CA) in May 2019.

    Interview

    1 phone interview. 6 rounds of 45 mins on-site interviews. They were very accommodating. The interviews were continuous except for a 30 mins lunch break after 3 rounds. the interview happened smoothly and on time.

    Interview Questions

    • Questions from my resume.
      Asked me to decipher a systemverilog design.
      Asked me to design a automated garage door.   Answer Question

  6.  

    IC Design Engineer Interview

    Anonymous Interview Candidate
    No Offer
    Neutral Experience
    Average Interview

    Application

    I applied through an employee referral. The process took 4 days. I interviewed at Xilinx.

    Interview

    He concentrated on clock tree synthesis, friendly. It was an interview with team manager. One question was unclear. He discussed resume and background in the first ten minutes. More of back end job.

    Interview Questions

    • Set up, hold times, multipliers   1 Answer

  7. Helpful (2)  

    Design Engineer Interview

    Anonymous Interview Candidate in San Jose, CA
    Declined Offer
    Positive Experience
    Average Interview

    Application

    I applied online. The process took 3 weeks. I interviewed at Xilinx (San Jose, CA) in March 2019.

    Interview

    Directly contacted by a member of the team for phone interview. After the phone interview, I was called on-site for 6 rounds of 45 minute sessions with teams members and a director, including HR round. The process was fast, with excellent transparency, and a very accommodating manager. The roles and the projects for the future were exciting but I decided to take a different offer.

    Interview Questions

    • Timing arcs, Perl script, Digital Design basics, FFs, Latches, SRAM.   1 Answer
  8.  

    Verification Design Engineer Interview

    Anonymous Employee in San Jose, CA
    Accepted Offer
    Positive Experience
    Average Interview

    Application

    I applied online. The process took 4+ weeks. I interviewed at Xilinx (San Jose, CA) in March 2019.

    Interview

    I applied online. The process took a month. One phone screen. The feeed back is generally given within a week. This is followed by five onsite interviews. The results are given in a week or two.

    Interview Questions

    • Verification of different designs. Some basic rtl design questions. Project related questions. UVM based questions   Answer Question

  9. Helpful (1)  

    Design Engineer Interview

    Anonymous Interview Candidate
    Declined Offer
    Positive Experience
    Average Interview

    Application

    I applied online. I interviewed at Xilinx.

    Interview

    interview i attend was an onsite interview at the head office. It is a great place to work. people are friendly and helpful.

    interview process conducted on time according to given schedule.

    Interview Questions


  10. Helpful (1)  

    Design Engineer Interview

    Anonymous Employee in San Jose, CA
    Accepted Offer
    Positive Experience
    Easy Interview

    Application

    I applied online. I interviewed at Xilinx (San Jose, CA) in January 2019.

    Interview

    1 Telephonic Interview + Day long On-site Interview Process(4 TIs + HR)

    Overall Topics to prepare:
    Digital(Muxes, FFs, Timing Params, Synchronizers and Asyn FIFOs, Clock domain crossings)
    Verilog Coding Basics (Case, if-else, Practical Design problems)
    SV Basics(Tasks Process, Fork Join)
    Comp Arch(Pipelining, Load store Arch)
    Scripting(Python/ Perl/ Tcl anyone)

    Interview Questions

    • #Telephonic Round:
      Simple digital, verilog, timing Qs (30mins)

      #Onsite Interview:(45 mins each)
      Round 1:
      Simple Digital Qs, Verilog code (Case , if-else difference, Blocking-Nonblocking difference, Unintensional latch problem), Power reduction techniques(Clk Gating) + extended Qs on same topic
      Previous work related Qs , Module's overall working

      Round 2:
      Verification basics like:
      What is fork -Join?
      Tasks and fns
      Pass by value , Pass by Refn
      Logic behind Linked list entry removal(How address pointer is changed)

      Round 3:
      Verilog code for shift left, shift right, parallel load functionality
      Some logical puzzales
      Digital concepts like basic gates using Mux, Gate Reduction etc.

      Round 4
      More on Power reduction
      Setup and Hold time eqs and Violation removal techniques
      Diffn betn: Glich and Jitter and skew   Answer Question

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