Process Integration Engineer Interview Questions

How can we reduce channel length modulation?

Create an arbitrary ternary phase diagram and explain it.

I was asked if I faced any problem in fabricating my devices and how i fixed those problems.

If suddenly all of your team members are on leave for some reasons and you're the only one to work, how would you manage your tasks ?

Be prepared to be at the dry erase board drawing graphs, explaining theory, or problem solving.

Factors that affect gate current ?

How does noise margin affected due to first order effect?

Diagram out an NFET, and how each component is fabricated.