Qualcomm Design Verification Engineer Interview Questions | Glassdoor

Qualcomm Design Verification Engineer Interview Questions

Updated Jun 26, 2017
9 Interview Reviews

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Design Verification Engineer Interview

Anonymous Interview Candidate in San Diego, CA
No Offer
Positive Experience
Average Interview

Application

I applied online. I interviewed at Qualcomm (San Diego, CA) in April 2017.

Interview

I applied through online qualcomm career portal and got an email 2 weeks later from HR,saying a staff engineer will call me for a phone technical interview.The phone interview was based on resume and lot of basic Systemverilog(writing assertion and constraints for different stimulus )/Verilog/Digital logic design questions.A week later received another email saying that I was selected for an onsite interview ( scheduled 2 weeks later).At onsite I had six (45-60 min each) one-on-one interviews with staff engineers .They said that result will be emailed two weeks later.

Interview Questions

  • 1)Should be ready to write some logics (C/Verilog/System Verilog) on the spot .
    2)Blocking and Non-Blocking.
    3)Fork/join types and applications.
    4)Test bench architecture blocks.(asked to write a generalized code to implement gen and
          bfm).   1 Answer

Other Interview Reviews for Qualcomm

  1. Helpful (1)  

    Verification Design Engineer Interview

    Anonymous Interview Candidate
    No Offer
    Positive Experience
    Average Interview

    Application

    I applied online. The process took 1 day. I interviewed at Qualcomm in November 2016.

    Interview

    I got an email for phone screen. Thoroughly asked all the project related questions in my resume. Also asked questions related to UVM since I had mentioned in my resume.

    Interview Questions


  2. Helpful (2)  

    Design Verification Engineer Interview

    Anonymous Interview Candidate
    No Offer
    Negative Experience
    Average Interview

    Application

    I applied online. The process took 3 weeks. I interviewed at Qualcomm.

    Interview

    Applied online on the job portal, Got a phone interview for the position of design verification engineer in Qualcomm QCT, Santa Clara. After phone interview was called upon for onsite interview which had 4-5 rounds. People who took interview were very detailed oriented and were looking for specific implementation details

    Interview Questions

    • All the questions were pretty basic and were related to fundamentals of logic design and verification.   Answer Question
  3. Helpful (1)  

    Design Verification Engineer Interview

    Anonymous Employee in Raleigh, NC
    Accepted Offer
    Positive Experience
    Average Interview

    Application

    I applied through an employee referral. The process took 2 weeks. I interviewed at Qualcomm (Raleigh, NC) in November 2014.

    Interview

    Two phone interviews - one with the manager, one with an engineer. First interview focused on previous relevant project experience (specific to hardware design projects). Second interview was broader about team projects and other software projects, to show experience. Interviewers were very supportive and shared a lot of information about their work and why they enjoy Qualcomm.

    Interview Questions


  4.  

    Design Verification Engineer Interview

    Anonymous Employee
    Accepted Offer

    Application

    I applied online. The process took a week. I interviewed at Qualcomm.

    Interview

    phone interview. asked systemverilog, a few quite easy questions on digital design

    Interview Questions


  5.  

    Design Verification Engineer Interview

    Anonymous Employee in Santa Clara, CA
    Accepted Offer
    Positive Experience
    Average Interview

    Application

    I applied through a staffing agency. The process took a week. I interviewed at Qualcomm (Santa Clara, CA) in June 2012.

    Interview

    Phone Interview. I was called on the phone. My background was discussed. Then, we discussed System Verilog constructs and Assertions. We also discussed random constraints in System Verilog.
    Then, I was told that they would get back to me. I got a call from the Staffing firm to tell me that I was selected.

    Interview Questions


  6.  

    Design Verification Engineer Interview

    Anonymous Interview Candidate in Markham, ON (Canada)
    Declined Offer
    Neutral Experience
    Difficult Interview

    Application

    I applied through an employee referral. The process took 2 weeks. I interviewed at Qualcomm (Markham, ON (Canada)) in February 2013.

    Interview

    Received phone call indicating they were interested in interviewing me followed by an email with a list of people I would interview with. The process was fairly disorganized with people coming and going at random times as the interview progressed with up to 8+ people in the room at certain times. Questions revolved around skills indicated on resume, and required drawing and coding on a whiteboard.

    Interview Questions

    • Write a decimal to hex function in C   1 Answer

  7.  

    Design Verification Engineer Interview

    Anonymous Interview Candidate in Toronto, ON (Canada)
    No Offer
    Neutral Experience
    Difficult Interview

    Application

    The process took 2 weeks. I interviewed at Qualcomm (Toronto, ON (Canada)) in December 2011.

    Interview

    I was contacted for a phone interview. I passed that and got an onsite interview the next week.
    Interview process was very technical. 10 people who asked questions for 5 hours.

    Interview Questions

    • Describe your design project in school   Answer Question
    • Know everything in c++. Virtual functions/class. Polymorphism. Be ready to write code on the spot   Answer Question
  8.  

    Design Verification Engineer Interview

    Anonymous Interview Candidate
    No Offer
    Neutral Experience
    Average Interview

    Application

    I applied online. The process took 2 weeks. I interviewed at Qualcomm in April 2011.

    Interview

    had a fone interview.

    Interview Questions


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